November 2006
rev 0.2
ASM2P5T9070A
2.5V Single Data Rate 1:10 Clock Buffer Terabuffer
Features
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Optimized for 2.5V LVTTL
Guaranteed Low Skew < 25pS (max)
Very low duty cycle distortion < 300pS (max)
High speed propagation delay < 2nS. (max)
Up to 200MHz operation
Very low CMOS power levels
Hot Insertable and over-voltage tolerant inputs
1:10 fanout buffer
2.5V Supply Voltage
Available in TSSOP Package
The ASM2P5T9070A 2.5V single data rate (SDR) clock
buffer is a single-ended input to ten single-ended outputs
buffer built on advanced metal CMOS technology. The
SDR clock buffer fanout from a single input to ten single-
ended outputs reduces the loading on the preceding driver
and provides an efficient clock distribution network.
The ASM2P5T9070A has two output banks that can be
asynchronously enabled/disabled. Multiple power and
grounds reduce noise.
Applications:
ASM2P5T9070A is targeted towards Clock and signal
distribution applications.
Functional Description
Block Diagram
GL
G1
OUTPUT
CONTROL
OUTPUT
CONTROL
OUTPUT
CONTROL
OUTPUT
CONTROL
OUTPUT
CONTROL
G2
OUTPUT
CONTROL
OUTPUT
CONTROL
OUTPUT
CONTROL
OUTPUT
CONTROL
OUTPUT
CONTROL
Q1
Q2
Q3
A
Q4
Q5
Q6
Q7
Q8
Q9
Q10
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200, Campbell, CA 95008
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Tel: 408-879-9077
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Fax: 408-879-9018
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
