November 2006
rev 0.3
Figure 3. Optimized Dual Line Termination
ASM2I99456 DUT
Differential
Pulse Generator
Z=50
Ω
Z
0
=50
Ω
Z
0
=50
Ω
ASM2I99456
R
T
=50
Ω
R
T
=50
Ω
V
TT
V
CC
– 2V
Figure 4. PCLK ASM2I99456 AC Test Reference for VCC = 3.3V and VCC = 2.5V
PCLK
V
CC
= 3.3V V
CC
= 2.5V
2.4
0.55
t
F
t
R
Q
X
t
P(LH)
t
P(HL)
1.8V
0.6V
PCLK
V
PP
V
CMR
V
CC
V
CC
÷2
GND
Figure 5. Output Transition Time Test Reference
Figure 6. Propagation Delay (t
PD
) Test Reference
V
CC
V
CC
÷2
GND
t
P
T
0
DC (t
P
÷T
0
Χ
100%)
V
CC
V
CC
÷2
GND
V
OH
V
CC
÷2
t
SK(LH)
t
SK(HL)
GND
The time from the output controlled edge to the
non-controlled edge, divided by the time output
controlled edge, expressed as a percentage.
The pin-to-pin skew is defined as the worst case
difference in propagation delay between any similar
delay path within a single device
Figure 8. Output-to- Output Skew t
SK(O)
Figure 7. Output Duty Cycle (DC)
V
CC
= 3.3V V
CC
= 2.5V
2.4
0.55
t
F
t
R
1.8V
0.6V
Figure 9. Output Transition Time Test Reference
3.3V/2.5V LVCMOS Clock Fanout Buffer
Notice: The information in this document is subject to change without notice.
8 of 14
PULSECORE [ PulseCore Semiconductor ]
