ASM2P5T905AG-28TR 参数 Datasheet PDF下载

November 2006

rev 0.2

DC Electrical Characteristics over Operating Range for 2.5V LVTTL

1

Symbol

Parameter

Input Characteristics

I

IH

I

IL

V

IK

V

IN

V

IH

V

IL

V

DIF

V

CM

V

IH

V

IL

V

REF

ASM2P5T905A

Test Conditions

V

DD

= 2.6V

V

I

= V

DDQ

/GND

V

DD

= 2.6V

V

I

= GND/V

DDQ

V

DD

= 2.4V, I

IN

= -18mA

Min

Typ

8

Max

±5

±5

- 1.2

+3.6

Unit

µA

V

V

V

V

V

Input HIGH Current

10

Input LOW Current

10

Clamp Diode Voltage

DC Input Voltage

2

- 0.7

-0.3

1.7

Single-Ended Inputs

DC Input HIGH

DC Input LOW

DC Differential Voltage

3,9

DC Common Mode Input

4,9

Voltage

DC Input HIGH

5,6,9

DC Input LOW

5,7,9

Single-Ended Reference

5,9

Voltage

Output HIGH Voltage

Output LOW Voltage

I

OH

= -12mA

I

OH

= -100µA

I

OL

= 12mA

I

OL

= 100µA

0.7

0.2

1150

V

REF

+ 100

V

REF

- 100

1250

1250

1350

Differential Inputs

mV

mV

mV

mV

V

V

V

V

Output Characteristics

V

OH

V

OL

V

DDQ

- 0.4

V

DDQ

- 0.1

0.4

0.1

NOTES:

1. See RECOMMENDED OPERATING RANGE table.

2. For 2.5V LVTTL single-ended operation, the RxS pin is tied HIGH and A/V

REF

is tied to GND.

3. V

DIF

specifies the minimum input differential voltage (V

TR

- V

CP

) required for switching where V

TR

is the "true" input level and V

CP

is the "complement" input

level. Differential mode only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential

voltage must be achieved to guarantee switching to a new state.

4. V

CM

specifies the maximum allowable range of (V

TR

+ V

CP

) /2. Differential mode only.

5. For single-ended operation, in differential mode, A/V

REF

is tied to the DC voltage V

REF

.

6. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.

7. Voltage required to maintain a logic LOW, single-ended operation in differential mode.

8. Typical values are at V

DD

= 2.5V, V

DDQ

= V

DD

, +25°C ambient.

9. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input interface

table should be referenced.

10. For differential mode (RxS = LOW), A and A/V

REF

must be at the opposite rail.

2.5V Single Data Rate 1:5 Clock Buffer Terabuffer

Notice: The information in this document is subject to change without notice.

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