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ASM3I622S00AF-08-SR 参数 Datasheet PDF下载

ASM3I622S00AF-08-SR图片预览
型号: ASM3I622S00AF-08-SR
PDF下载: 下载PDF文件 查看货源
内容描述: 低频定时- SAFE™峰值EMI降低IC [Low Frequency Timing-Safe™ Peak EMI reduction IC]
分类和应用: 晶体时钟发生器微控制器和处理器外围集成电路光电二极管
文件页数/大小: 16 页 / 712 K
品牌: PULSECORE [ PulseCore Semiconductor ]
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May 2007
rev 0.4
ASM3P622S00A/B/J/E/K
Low Frequency Timing-Safe™ Peak EMI reduction IC
General Features
Low Frequency Clock distribution with Timing-
Safe™ Peak EMI Reduction
Input frequency range: 4MHz - 20MHz
Zero input - output propagation delay
Low-skew outputs
Output-output skew less than 250pS
Device-device skew less than 700pS
Less than 200pS cycle-to-cycle jitter
Available in 16pin, 150mil SOIC, 4.4mm TSSOP
(ASM3P622S00E/K), and in 8pin, 150 mil SOIC,
4.4mm TSSOP Packages (ASM3P622S00A/B/J)
3.3V Operation
Industrial temperature range
Advanced CMOS technology
The First True Drop-in Solution
one reference input and drives out one low-skew clock.
All parts have on-chip PLLs that lock to an input clock on
the XIN/CLKIN pin. The PLL feedback is on-chip and is
obtained from the CLKOUT pad, internal to the device.
Multiple ASM3P622S00E/K devices can accept the same
input clock and distribute it. In this case, the skew between
the outputs of the two devices is guaranteed to be less than
700pS.
All outputs have less than 200pS of Cycle-to-cycle jitter.
The input and output propagation delay is guaranteed to be
less than ±350pS, and the output-to-output skew is
guaranteed to be less than 250pS.
Refer
Spread Spectrum Control and Input-Output Skew
Functional Description
ASM3P622S00A/B/J/E/K is a versatile, 3.3V Zero-delay
buffer designed to distribute low frequency Timing-Safe™
clocks with Peak EMI reduction. ASM3P622S00E/K
accepts one reference input and drives out eight low-skew
clocks.
It
is
available
in
a
16pin
Package.
The
ASM3P622S00A/B/J is the eight-pin version and accepts
Table”
for
deviations
and
Input-Output
Skew for
ASM3P622S00A/B/J and ASM3P622S00E/K devices
The ASM3P622S00A/B/J and ASM3P622S00E/K are
available in two different packages, as shown in the
ordering information table.
Block Diagram
V
DD
SSON
SS%
Modulation
XIN/CLKIN
XOUT
Crystal
Oscillator
Reference
Divider
Feedback
Divider
Phase
Detector
Loop
Filter
PLL
VCO
Feedforward
Divider
CLKOUT
GND
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200 Campbell, CA 95008
Tel: 408-879-9077
Fax: 408-879-9018
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.