May 2007
rev 0.4
Operating Conditions for ASM3P622S00A/B/J/E/K Devices
Parameter
VDD
T
A
C
L
C
IN
Supply Voltage
Operating Temperature (Ambient Temperature)
Load Capacitance
Input Capacitance
ASM3P622S00A/B/J/E/K
Description
Min
3.0
-40
Max
3.6
+85
30
7
Unit
V
°C
pF
pF
Electrical Characteristics for ASM3P622S00A/B/J/E/K
Parameter
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
I
DD
Z
o
Description
Input LOW Voltage
1
Input HIGH Voltage
1
Input LOW Current
Input HIGH Current
Output LOW Voltage
2
Output HIGH Voltage
2
Supply Current
Output Impedance
V
IN
= 0V
Test Conditions
Min
2.0
Typ
Max
0.8
50
100
0.4
Unit
V
V
µA
µA
V
V
mA
Ω
V
IN
= VDD
I
OL
= 8mA
I
OH
= -8mA
Unloaded outputs
2.4
15
23
Note: 1. CLKIN input has a threshold voltage of VDD/2
2. Parameter is guaranteed by design and characterization. Not 100% tested in production
Switching Characteristics for ASM3P622S00A/B/J/E/K
1
Parameter
1/t
1
t
3
t
4
t
5
t
6
t
7
t
J
t
LOCK
Description
Output Frequency
Duty Cycle
2
= (t
2
/ t
1
) * 100
Output Rise Time
2
Output Fall Time
2
Output-to-output skew
2
Delay, CLKIN Rising Edge to
CLKOUT Rising Edge
2
Test Conditions
30pF load
Measured at VDD/2
Measured between 0.8V and 2.0V
Measured between 2.0V and 0.8V
All outputs equally loaded
Measured at VDD /2
Measured at VDD/2 on the CLKOUT pins
of the device
Loaded outputs
Stable power supply, valid clock presented
on CLKIN pin
Min
4
40
Typ
50
Max
20
60
2.5
2.5
250
±350
700
200
1.0
Unit
MHz
%
nS
nS
pS
pS
pS
pS
mS
Device-to-Device Skew
2
Cycle-to-cycle jitter
2
PLL Lock Time
2
Note: 1. All parameters specified with loaded outputs.
2. Parameter is guaranteed by design and characterization. Not 100% tested in production
Low Frequency Timing-Safe™ Peak EMI Reduction IC
Notice: The information in this document is subject to change without notice.
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PULSECORE [ PulseCore Semiconductor ]
