RDC
®
RISC DSP Communication
R2886
FAST ETHERNET RISC PROCESSOR
1.
Features
l
CPU Core
- RDC’s proprietary RISC architecture
- Five-stage pipeline architecture
- Operation frequency: 150MHz
- Supports a 16K-byte uniform cache
l
ROM/RAM/SDRAM Controller and Addressing
Space
- Supports 16-bit data bus width
- Flash ROM/SRAM control interface
- SDRAM control interface
- 16M addressing space
- 64K-byte I/O space
l
Two Independent DMA Controllers
- Supports high-speed DMA transfers
l
Interrupt Controller
- Provides 8 maskable external interrupt channels
l
Counter/Timers
- Three independent programmable 16-bit timers
- One programmable watchdog timer which can
generate NMI or reset
l
High Performance UART Ports
- Supports 2 high performance UARTs with
send/receive 16-byte FIFOs
- Programmable baud rate generator
- The data rates are programmable from 50 to
460.8K baud (max. to 1Mbps)
- The character options are programmable for 1 start
bit; 1, 1.5 or 2 stop bits; even, odd or no parity, 5~8
data bits
l
RDC Debug Tool Support
- RDC debug tool with a JTAG-like interface
l
General Programmable I/O
- 64 programmable I/O ports
- Pins individually configurable to input or output
mode
l
Two 10/100M Fast Ethernet MAC Ports
- IEEE 802.3u MII interface
- IEEE 802.3x flow control in full-duplex mode
- Internal loop-back self-test circuit support
- Descriptor architecture for packet TX/RX
l
PCI Control Interface Support
- Supports up to 3 PCI masters
- Speed up to 33MHz
l
Two Card Bus Interface Support
l
Two USB 2.0 Host Port Support
- Supports HS, FS and LS
l
Package Type
- With 128-pin PQFP & LFBGA-225 package type
l
A Green Product
Specifications subject to change without notice, contact your sales representatives for the most update information.
Page
2 of
5
REV
1.0
Aug.25 2006
RDC [ RDC SEMICONDUCTOR ]
