RDC
®
RISC DSP Communication
R2886
FAST ETHERNET RISC PROCESSOR
2.
Block Diagram
CLKOUTA
SD_CLK
PCICLK
INTB_n
INTA_n
INT3
INT2
INT1
INT0
DRQ0/INT5 DRQ1/INT6
VCC
GND
X1
X2
Clock & Power
Management Uuit
Interrupt
Controller
Unit
Timer
Controller
Unit
DMA
Controller
Unit
RST_n
Reset Unit
PCIRST_n
MAC 0
MII 0
UCS_n
MCS_n
PCS0_n
PCS1_n
PCS2_n
PCS3_n
PCS5_n
PCS6_n
MAC 1
Chip
Select
Unit
RDC
RISC CPU
16K-B yte
L1 Cache
P CI Master
PCI Bus Interface
Refresh
Control Unit
P CI Target
PIO Unit
MII 1
PIO[63:0]
16550 UART
Serial Port 0
UART0
RAS_n
CAS_n
WE_n
DQMH
DQML
BA[1:0]
16550 UART
Serial Port 1
UART1
SDRAM/B us Interface
Unit
P CI Configuration
Register
P CI Arbiter
Port 0
USB 2.0
Host
Port 1
DP0, DM0
DP1, DM1
A[22:0]
D[15:0]
RD_n
IOW_n
IOR_n
ARDY
WR_n
PCIBus
OVRCUR_n
Specifications subject to change without notice, contact your sales representatives for the most update information.
Page
3 of
5
REV
1.0
Aug.25 2006
RDC [ RDC SEMICONDUCTOR ]
