HD74HC164
8-bit Parallel-out Shift Register
REJ03D0580-0300
Rev.3.00
Jan 31, 2006
Description
This 8-bit shift register has gated serial inputs and clear. Each register bit is a D-type master/slave flip-flop. Inputs A
& B permit complete control over the incoming data. A low at either or both inputs inhibits entry of new data and
resets the first flip-flop to the low level at the next clock pulse. A high level on the input enables the other input which
will then determine the state of the first flip-flop. Data at the serial inputs may be changed while the clock is high or
low, but only information meeting the setup and hold time requirements will be entered. Data is serially shifted in and
out of the 8-bit register during the positive going transition of the clock pulse. Clear is independent of the clock and
accomplished by a low level at the clear input.
Features
•
•
•
•
•
•
High Speed Operation: t
pd
(Clock to Q) = 14.5 ns typ (C
L
= 50 pF)
High Output Current: Fanout of 10 LSTTL Loads
Wide Operating Voltage: V
CC
= 2 to 6 V
Low Input Current: 1
µA
max
Low Quiescent Supply Current: I
CC
(static) = 4
µA
max
Ordering Information
Part Name
HD74HC164P
HD74HC164FPEL
Package Type
DILP-14 pin
SOP-14 pin (JEITA)
Package Code
(Previous Code)
PRDP0014AB-B
(DP-14AV)
PRSP0014DF-B
(FP-14DAV)
Package
Abbreviation
P
FP
—
EL (2,000 pcs/reel)
Taping Abbreviation
(Quantity)
Note: Please consult the sales office for the above package availability.
Function Table
Inputs
Clear
L
H
H
H
H
Clock
X
A
X
X
L
X
H
B
X
X
X
L
H
Q
A
L
Q
Ao
L
L
H
Q
B
L
Q
Bo
Q
An
Q
An
Q
An
Outputs
·········
·········
·········
·········
·········
·········
Q
H
L
Q
Ho
Q
Gn
Q
Gn
Q
Gn
Q
Ao
to Q
Ho
= Outputs remain unchanged.
Q
An
to Q
Gn
= Data shifted from the previous stage on a positive edge at the clock input.
H:
High level
L:
Low level
X:
Irrelevant
Rev.3.00, Jan 31, 2006 page 1 of 6
RENESAS [ RENESAS TECHNOLOGY CORP ]
