HD74HC165
Parallel-load 8-bit Shift Register
REJ03D0581-0300
Rev.3.00
Jan 31, 2006
Description
This 8-bit serial shift register shifts data from Q
A
to Q
H
when clocked. Parallel inputs to each stage are enabled by a
low level at the Shift/Load input. Also included is a gated clock input and a complementary output from the eighth bit.
Clocking is accomplished through a 2-input NOR gate permitting one input to be used as a clock inhibit function.
Holding either of the clock inputs high inhibits clocking, and holding either clock input low with the Shift/Load input
high enables the other clock input. Data transfer occurs on the positive going edge of the clock. Parallel loading is
inhibited as long as the Shift/Load input is high. When taken low, data at the parallel inputs is loaded directly into the
register independent of the state of the clock.
Features
•
•
•
•
•
•
High Speed Operation: t
pd
(Clock to Q
H
) = 21 ns typ (C
L
= 50 pF)
High Output Current: Fanout of 10 LSTTL Loads
Wide Operating Voltage: V
CC
= 2 to 6 V
Low Input Current: 1
µA
max
Low Quiescent Supply Current: I
CC
(static) = 4
µA
max (Ta = 25°C)
Ordering Information
Part Name
HD74HC165P
HD74HC165FPEL
Package Type
DILP-16 pin
SOP-16 pin (JEITA)
Package Code
(Previous Code)
PRDP0016AE-B
(DP-16FV)
PRSP0016DH-B
(FP-16DAV)
Package
Abbreviation
P
FP
—
EL (2,000 pcs/reel)
Taping Abbreviation
(Quantity)
Note: Please consult the sales office for the above package availability.
Function Table
Inputs
Parallel
Shift/Load
Clock Inhibit
Clock
Serial
A ······ H
Internal outputs
Q
A
Q
B
b
Q
B0
Q
An
Q
An
Q
B0
Output
Q
H
h
Q
H0
Q
Gn
Q
Gn
Q
H0
L
X
X
X
a ······h
a
H
L
L
X
X
Q
A0
H
X
H
H
L
L
X
L
H
L
H
H
X
X
X
Q
A0
Q
Ao
to Q
Ho
= Outputs remain unchanged.
Q
An
to Q
Gn
= Data shifted from the previous stage on a positive edge at the clock input.
H:
High level
L:
Low level
X:
Irrelevant
Rev.3.00, Jan 31, 2006 page 1 of 7