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HD74HC595FPEL 参数 Datasheet PDF下载

HD74HC595FPEL图片预览
型号: HD74HC595FPEL
PDF下载: 下载PDF文件 查看货源
内容描述: 8位移位寄存器/锁存( 3态输出) [8-bit Shift Register/Latch (with 3-state outputs)]
分类和应用: 移位寄存器
文件页数/大小: 11 页 / 114 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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HD74HC595
8-bit Shift Register/Latch (with 3-state outputs)
REJ03D0634-0200
(Previous ADE-205-514)
Rev.2.00
Mar 30, 2006
Description
This device each contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The
storage register has parallel 3-state outputs. Separate clocks are provided for both the shift register and the storage
register. The shift register has a direct-overriding clear, serial input, and serial output pins for cascading.
Both the shift register and storage register clocks are positive-edge triggered. If the user wishes to connect both clocks
together, the shift register state will always be one clock pulse ahead of the storage register.
Features
High Speed Operation: t
pd
(RCK to Q) = 17 ns typ (C
L
= 50 pF)
High Output Current: Fanout of 15 LSTTL Loads (Q
A
to Q
H
outputs)
Wide Operating Voltage: V
CC
= 2 to 6 V
Low Input Current: 1
µA
max
Low Quiescent Supply Current: I
CC
(static) = 4
µA
max (Ta = 25°C)
Ordering Information
Part Name
HD74HC595P
HD74HC595FPEL
Package Type
DILP-16 pin
SOP-16 pin (JEITA)
Package Code
(Previous Code)
PRDP0016AE-B
(DP-16FV)
PRSP0016DH-B
(FP-16DAV)
P
FP
Package
Abbreviation
EL (2,000 pcs/reel)
Taping Abbreviation
(Quantity)
Note: Please consult the sales office for the above package availability.
Function Table
Inputs
RCK
X
X
X
SCK
X
X
X
SCLR
X
L
H
H
G
H
X
X
X
Function
Q
A
to Q
H
high impedance
Shift register cleared Q
H
’ = L
Shift register clocked Q
n
= Q
n – 1
, Q
A
= SER
Contents of shift register transferred to output latches
Rev.2.00 Mar 30, 2006 page 1 of 10