HD74LS273
Octal D-type Positive-edge-triggered Flip-Flops (with Clear)
REJ03D0473–0300
Rev.3.00
Jul.15.2005
The HD74LS273, positive-edge-triggered flip-flops utilize LS TTL circuitry to implement D-type flip-flop logic with a
direct clear input.
Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going
edge of the clock pulse.
When the clock input is at either the high or low level, the D input signal has no effect at the output.
Features
•
Ordering Information
Part Name
HD74LS273P
HD74LS273FPEL
HD74LS273RPEL
Package Type
DILP-20 pin
SOP-20 pin (JEITA)
SOP-20 pin (JEDEC)
Package Code
(Previous Code)
PRDP0020AC-B
(DP-20NEV)
PRSP0020DD-B
(FP-20DAV)
Package
Abbreviation
P
FP
Taping Abbreviation
(Quantity)
—
EL (2,000 pcs/reel)
EL (1,000 pcs/reel)
PRSP0020DC-A
RP
(FP-20DBV)
Note: Please consult the sales office for the above package availability.
Pin Arrangement
Clear
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
1
2
3
4
5
6
7
8
9
10
Q
Clear
D CK
D
Q
Q
CK
Clear
Q
Clear
CK D
CK D
Clear
Q
Q
Clear
CK D
CK D
Clear
Q
20
19
18
17
16
15
14
13
12
11
V
CC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
Clock
Clear
D CK
D
CK
Clear
Q
(Top view)
Rev.3.00, Jul.15.2005, page 1 of 6
RENESAS [ RENESAS TECHNOLOGY CORP ]
