Ver. 1.1
MITSUBISHI LSIs
M5M51008DFP,VP,RV,KV,KR -55H, -70H
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS
(Ta=0~70°C, 5V±10% unless otherwise noted )
(1) MEASUREMENT CONDITIONS
Input pulse level ............... V
IH
=2.4V,V
IL
=0.6V (-70H)
V
IH
=3.0V,V
IL
=0.0V (-55H)
...... 5ns
Input rise and fall time
Reference level ................ V
OH
=V
OL
=1.5V
Output loads ..................... Fig.1, C
L
=100pF (-70H)
C
L
=30pF (-55H)
C
L
=5pF (for t
en
,t
dis
)
Transition is measured ± 500mV from steady
state voltage. (for t
en
,t
dis
)
V
CC
1.8kΩ
DQ
990Ω
C
L
( Including scope
and JIG )
Fig.1 Output load
(2) READ CYCLE
Limits
Symbol
t
CR
t
a(A)
t
a(S1)
t
a(S2)
t
a(OE)
t
dis(S1)
t
dis(S2)
t
dis(OE)
t
en(S1)
t
en(S2)
t
en(OE)
t
V(A)
Parameter
Read cycle time
Address access time
Chip select 1 access time
Chip select 2 access time
Output enable access time
Output disable time after S
1
high
Output disable time after S
2
low
Output disable time after OE high
Output enable time after S
1
low
Output enable time after S
2
high
Output enable time after OE low
Data valid time after address
Min
55
-55H
Max
55
55
55
30
20
20
20
5
5
5
5
10
10
5
10
Min
70
-70H
Max
70
70
70
35
25
25
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
(3) WRITE CYCLE
Limits
Symbol
t
CW
t
w(W)
t
su(A)
t
su(A-WH)
t
su(S1)
t
su(S2)
t
su(D)
t
h(D)
t
rec(W)
t
dis(W)
t
dis(OE)
t
en(W)
t
en(OE)
Parameter
Write cycle time
Write pulse width
Address setup time
Address setup time with respect to W
Chip select 1 setup time
Chip select 2 setup time
Data setup time
Data hold time
Write recovery time
Output disable time from W low
Output disable time from OE high
Output enable time from W high
Output enable time from OE low
-55H
Min
Max
55
45
0
50
50
50
25
0
0
20
20
5
5
5
5
-70H
Min
Max
70
50
0
55
55
55
30
0
0
25
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
RENESAS [ RENESAS TECHNOLOGY CORP ]
