M62429P/FP
Relationship between Data and Clock
CLOCK
DATA
D0
D1
D2
D3
D8
D9
D10
Latch signal "H"
Reads data signal at the rising edge of clock signal
Reads latch signal at the falling edge of clock
DC Characteristics of Digital Block
Item
"L" level input voltage
"H" level input voltage
"L" level input current
"H" level input current
Symbol
V
IL
V
IH
I
IL
I
IH
Min
0
0.8 V
CC
–10
—
Limits
Typ
~
~
—
—
Max
0.2 V
CC
V
CC
10
10
Unit
V
V
µA
µA
Test Conditions
Data, clock pin
V
I
= 0
V
I
= 5 V
Data, clock pin
AC Characteristics of Digital Block
Item
Cycle time of clock
Pulse width of clock ("H" level)
Pulse width of clock ("L" level)
Clock rising time
Clock falling time
Data setup time
Data hold time
Symbol
t
cr
t
WHC
t
WLC
t
r
t
f
t
SD
t
HD
Min
4
1.6
1.6
—
—
0.8
0.8
Limits
Typ
—
—
—
—
—
—
—
Max
—
—
—
0.4
0.4
—
—
Unit
µs
µs
µs
µs
µs
µs
µs
Clock and Data Timing
t
cr
75%
CLOCK
25%
t
r
t
WHC
t
f
t
WLC
DATA
t
SD
t
HD
REJ03F0209-0300 Rev.3.00 Jun 15, 2007
Page 4 of 8
RENESAS [ RENESAS TECHNOLOGY CORP ]
