M66255FP
8192
×
10-Bit Line Memory (FIFO)
REJ03F0249-0200
Rev.2.00
Sep 14, 2007
Description
The M66255FP is a high-speed line memory with a FIFO (First In First Out) structure of 8192-word
×
10-bit
configuration which uses high-performance silicon gate CMOS process technology.
It has separate clock, enable and reset signals for write and read, and is most suitable as a buffer memory between
devices with different data processing throughput.
Features
•
•
•
•
•
•
•
Memory configuration:
8192 words
×
10 bits (dynamic memory)
High-speed cycle:
30 ns (Min)
High-speed access:
25 ns (Max)
Output hold:
5 ns (Min)
Fully independent, asynchronous write and read operations
Variable length delay bit
Output:
3 states
Application
Digital photocopiers, high-speed facsimile, laser beam printers.
Block Diagram
Data input
D
0
to D
9
15
16
17
18
19
24
25
26
27
28
1
Data output
Q
0
to Q
9
2
3
4
5
10
11
12
13
14
Input buffer
Output buffer
Read address counter
Write address counter
Read control circuit
Write control circuit
WE
23
Write
enable input
WRES
22
Write
reset input
WCK 20
Write
clock input
V
CC
21
6
RE
Read
enable input
Memory array of
8192-word
×
10-bit
configuration
7
RRES
Read
reset input
9
RCK
Read
clock input
8
GND
REJ03F0249-0200 Rev.2.00 Sep 14, 2007
Page 1 of 13
RENESAS [ RENESAS TECHNOLOGY CORP ]
