R32C/116A Group
1. Overview
1.4
Pin Assignments
Figure 1.3 and Figure 1.4 show the pin assignments (top view) and Table 1.6 to Table 1.13 show the pin
characteristics.
(Note 1)
(Note 2)
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
IIO0_0 / IIO1_0 / D8 / P1_0
P4_4 / CS3 / A20 / CTS6 / RTS6 / SS6
AN0_7 / D7 / P0_7
P4_5 / CS2 / A21 / CLK6
AN0_6 / D6 / P0_6
P4_6 / CS1 / A22 / RXD6 / SCL6 / STXD6
AN0_5 / D5 / P0_5
P4_7 / CS0 / A23 / TXD6 / SDA6 / SRXD6
AN0_4 / D4 / P0_4
P19_2
P19_1
P17_0
WR3 / BC3 / P11_4
P17_1
P19_0
P17_2
IIO1_3 / CTS8 / RTS8 / WR2 / CS3 / P11_3
P17_3
IIO1_2 / RXD8 / CS2 / P11_2
P19_3
IIO1_1 / CLK8 / CS1 / P11_1
P12_5 / D21
P12_6 / D22
P12_7 / D23
P5_0 / WR0 / WR
P5_1 / WR1 / BC1
P5_2 / RD
IIO1_0 / TXD8 / CS0 / P11_0
P18_7
P18_6
P18_5
P18_4
P18_3
P5_3 / CLKOUT / BCLK
P13_0 / D24 / OUTC2_4
P13_1 / D25 / OUTC2_5
VCC
P18_2
AN0_3 / D3 / P0_3
R32C/116A GROUP
AN0_2 / D2 / P0_2
AN0_1 / D1 / P0_1
P13_2 / D26 / OUTC2_6
(Note 2)
AN0_0 / D0 / P0_0
VSS
PLQP0176KB-A
(176P6Q-A)
(Top view)
IIO0_7 / CTS6 / RTS6 / SS6 / AN15_7 / P15_7
IIO0_6 / CLK6 / AN15_6 / P15_6
IIO0_5 / RXD6 / SCL6 / STXD6 / AN15_5 / P15_5
IIO0_4 / TXD6 / SDA6 / SRXD6 / AN15_4 / P15_4
IIO0_3 / CTS7 / RTS7 / AN15_3 / P15_3
IIO0_2 / RXD7 / AN15_2 / P15_2
IIO0_1 / CLK7 / AN15_1 / P15_1
VSS
P13_3 / D27 / OUTC2_3
P5_4 / HLDA / CS1 / TXD7
P5_5 / HOLD / CLK7
P5_6 / ALE / CS2 / RXD7
P5_7 / RDY / CS3 / CTS7 / RTS7
P19_4
P13_4 / D28 / OUTC2_0 / ISTXD2 / IEOUT
P13_5 / D29 / OUTC2_2 / ISRXD2 / IEIN
P13_6 / D30 / OUTC2_1 / ISCLK2
P13_7 / D31 / OUTC2_7
IIO0_0 / TXD7 / AN15_0 / P15_0
VCC
KI3 / AN_7 / P10_7
P19_5
KI2 / AN_6 / P10_6
P6_0 / TB0IN / CTS0 / RTS0 / SS0
P6_1 / TB1IN / CLK0
KI1 / AN_5 / P10_5
KI0 / AN_4 / P10_4
P6_2 / TB2IN / RXD0 / SCL0 / STXD0
P6_3 / TXD0 / SDA0 / SRXD0
P6_4 / CTS1 / RTS1 / SS1 / OUTC2_1 / ISCLK2
P6_5 / CLK1
AN_3 / P10_3
AN_2 / P10_2
AN_1 / P10_1
AVSS
P11_7
AN_0 / P10_0
P6_6 / RXD1 / SCL1 / STXD1
P14_7
VREF
AVCC
P6_7 / TXD1 / SDA1 / SRXD1
P7_0 / TA0OUT / TXD2 / SDA2 / SRXD2 / IIO1_6 / OUTC2_0 / ISTXD2 / IEOUT / MSDA
STXD4 / SCL4 / RXD4 / ADTRG / P9_7
(Note 3)
(Note 2)
Notes:
1. Pin names in brackets [ ] represent a functional signal as a whole and should not be considered as two separate pins.
2. The following pins are 5 V tolerant inputs: P4_0 to P4_7, P5_4 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_3, P12_0 to P12_7, P16_0 to P16_7, and P17_0 to P17_3.
3. The position of pin number 1 varies by product. Refer to the index mark in attached “Package Dimensions”.
Figure 1.3
Pin Assignment for the 176-pin Package (top view)
REJ03B0297-0100 Rev.1.00
Jul 16, 2010
Page 9 of 99
RENESAS [ RENESAS TECHNOLOGY CORP ]
