RQJ0201UGDQA
Silicon P Channel MOS FET
Power Switching
REJ03G1317-0300
Rev.3.00
May 24, 2006
Features
•
Low on-resistance
R
DS(on)
= 53 mΩ typ (V
GS
= –4.5 V, I
D
= –1.8 A)
•
Low drive current
•
High speed switching
•
2.5 V gate drive
Outline
RENESAS Package code: PLSP0003ZB-A
(Package name: MPAK)
3
D
3
1
2
2
G
1. Source
2. Gate
3. Drain
S
1
Note:
Marking is “UG”.
Absolute Maximum Ratings
(Ta = 25°C)
Item
Symbol
Drain to source voltage
V
DSS
Gate to source voltage
V
GSS
Drain current
I
D
Note1
Drain peak current
I
D(pulse)
Body - drain diode reverse drain current
I
DR
Channel dissipation
Pch
(pulse) Note2
Channel temperature
Tch
Storage temperature
Tstg
Notes: 1. PW
≤
10
µs,
duty cycle
≤
1%
2. When using the glass epoxy board (FR-4: 40 x 40 x 1 mm)
Ratings
–20
+8 / –12
–3.4
–10
–3.4
0.8
150
–55 to +150
Unit
V
V
A
A
A
W
°C
°C
Rev.3.00 May 24, 2006 page 1 of 6