LM358DT/PT/ST/WDT/WPT,LM2904DT/PT/ST/WDT/WPT
LM324DT/PT/WDT,LM2902DT/PT/WDT
●Circuit
Diagram
Vcc
+
Technical Note
INVERTING
INPUT
OUTPUT
NON-INVERTING
INPUT
Vcc
-
Fig.97 Circuit Diagram (each Op-Amp)
●Measurement
Circuit 1 NULL Method Measurement Condition
Vcc , Vcc , EK, Vicm Unit: [V]
LM358/LM324 family
LM2904/LM2902 family
Calculation
Vcc+ Vcc- EK Vicm Vcc+ Vcc- EK Vicm
0
0
0
0
0
0
0
0
0
0
-1.4
-1.4
-1.4
-1.4
-1.4
-11.4
-1.4
-1.4
-1.4
-1.4
0
0
0
0
0
0
0
3.5
0
0
5 to 30
5
5
5
15
15
5
5
5
30
0
0
0
0
0
0
0
0
0
0
-1.4
-1.4
-1.4
-1.4
-1.4
-11.4
-1.4
-1.4
-1.4
-1.4
0
0
0
0
0
0
0
3.5
0
0
1
2
3
4
5
6
5
5
5
15
15
5
5
5
30
+
-
Parameter
Input Offset Voltage
Input Offset Current
Input Bias Current
Large Signal Voltage Gain
Common-mode Rejection Ratio
Supply Voltage Rejection Ratio
VF
S1
S2
S3
VF1 ON ON OFF 5 to 30
VF2 OFF OFF OFF
VF3 OFF ON
VF4 ON OFF
VF5
VF6
VF7
VF8
VF9
VF10
ON
ON
ON
OFF
ON ON
ON OFF
ON OFF
－Calculation－
1. Input Offset Voltage (VIO)
VF1
Vio
�½
1+ Rf /Rs [V]
0.1[μF]
2. Input Offset Current (IIO)
Iio
�½
VF2 - VF1 [A]
Ri (1+ Rf / Rs)
S1
Rs
Vicm
Ri
Vcc
+
Rf
50[kΩ]
500[kΩ]
VOUT EK
0.1[μF]
3. Input Bias Current (IIB)
VF4 - VF3
[A]
Ib
�½
2× Ri (1+ Rf / Rs)
+15[V]
500[kΩ]
DUT
S3
1000[pF]
Vcc
-
50[Ω] 10[kΩ]
50[Ω] 10[kΩ]
Rs
Ri
S2
Rf
50[kΩ]
4. Large Signal Voltage Gain (AVD)
AV
�½
20× Log 10× (1+ Rf /Rs) [dB]
VF6 - VF5
RL
-15[V]
V
VF
5.Common-mode Rejection Ration (CMRR)
CMRR
�½
20× Log 3.5× (1+ Rf/ Rs)
VF8-VF7
[dB]
6. Supply Voltage Rejection Ration (SVR)
PSRR
＝
20×Log
△
Vcc
+
×(1+Rf/Rs)
VF10 - VF9
[dB]
Fig.98 Measurement circuit1 (Each Op-Amps)
△
Vcc
+
=25V
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12/17
2011.06 - Rev.B
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