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SA9604APA 参数 Datasheet PDF下载

SA9604APA图片预览
型号: SA9604APA
PDF下载: 下载PDF文件 查看货源
内容描述: 三相双向功率/电能计量具有串行SPI接口IC [THREE PHASE BIDIRECTIONAL POWER/ENERGY METERING IC WITH SERIAL SPI INTERFACE]
分类和应用:
文件页数/大小: 20 页 / 109 K
品牌: SAMES [ SAMES ]
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SA9604A
4.
Power Consumption
The power consumption rating of the SA9604A integrated circuit is less than 50mW.
5.
SPI - INTERFACE
5.1 Description
The serial peripheral interface (SPI) is a synchronous bus for data transfer and is
used when interfacing the SA9604A with any micro-controller. Four pins are used
for the SPI. The four pins are DO (Serial Data Out), DI (Serial Data In), CE (Chip
Enable), and SCK (Serial Clock). The SA9604A is the slave device in an SPI
application, with the micro-controller being the master. The DI and DO pins are the
serial data input and output pins for the SA9604A, respectively. The CE input is used
to initiate and terminate a data transfer. The SCK pin is used to synchronize data
movement between the master (micro-controller) and the slave (SA9604A) devices.
The serial clock (SCK), which is generated by the micro-controller, is active only
during address and data transfer to any device on the SPI bus.
5.2 Register Access
There are four registers for each phase which can be read: active, reactive, voltage
and frequency. Any of these registers may be chosen as the initial register to read.
If the SCK clock input continues after the first register has been read, the contents
of subsequent registers will be output on the DO pin. Transfer will continue until CS
is brough inactive.
To enable registers for reading, the sequence 1 1 0 (6
HEX
) must precede the 6 bit
address of the register being accessed.
The various register addresses are shown in the table below:
ID
1
2
3
4
5
6
7
8
9
10
11
12
6/20
REGISTER
Active:
Reactive:
Voltage:
Frequency:
Active:
Reactive:
Voltage:
Frequency:
Active:
Reactive:
Voltage:
Frequency:
sames
Phase 1
Phase 1
Phase 1
Phase 1
Phase 2
Phase 2
Phase 2
Phase 2
Phase 3
Phase 3
Phase 3
Phase 3
A5
X
X
X
X
X
X
X
X
X
X
X
X
A4
X
X
X
X
X
X
X
X
X
X
X
X
A3
0
0
0
0
0
0
0
0
1
1
1
1
A2
0
0
0
0
1
1
1
1
0
0
0
0
A1
0
0
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1