SA9903B
sames
The sequence 110 (0x06) must precede the 6-bit address of
the register being accessed. When CS is HIGH, data on pin DI
is clocked into the SA9903B on the rising edge of SCK. Figure
5 shows the data clocked into DI comprising of 1 1 0 A5 A4 A3
A2 A1 A0.
Address locations A5 and A4 are included for compatibility with
future developments.
Registers may be read individually and in any order. After a
register has been read, the contents of the next register value
will be shifted out on the DO pin with every SCK clock cycle.
Data output on DO will continue until CS is inactive.
The 9 bits needed for register addressing can be padded with
leading zeros when the micro-controller requires a 8 bit SPI
word length. The following sequence is valid:
0000 0001 10A5A4
A3A2A1A0
SCK
t3
t4
DI
t2
t5
DO
t1
CS
DR-01545
Parameter Description
t1
t3
t4
t2
SCK rising edge to DO valid
SCK min high time
SCK min low time
Setup time for DI and CS
Min
Max
625ns 1.160µs
625ns
625ns
DATA FORMAT
Figure 5 shows the SPI waveforms. After the least significant
digit of the address has been entered on the rising edge of
SCK, the output DO goes low with the falling edge of SCK.
Each subsequent falling edge transition on the SCK pin will
validate the next data bit on the DO pin.
The content of each register consists of 24 bits of data. The
MSB is shifted out first.
before the rising edge of SCK 20ns
t5
DI hold time
625ns
Figure 6: SPI Timing diagrams with timing information
SCK
CS
Read command
DI
DO
0
1
1
0
Register address
A5
A4
A3
A2
A1
A0
Register Data
D23
D22
D21
D1
D0
Next data register
D23
D22
D1
D0
High impedance
Figure 5: SPI waveforms
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SAMES [ SAMES ]
