Si500S
Parameters
Condition
1.8 V option, 40 pF, 40 MHz, CMOS
1.8 V option, 10 pF, 200 MHz, CMOS
2.5 V option, 40 pF, 40 MHz, CMOS
2.5 V option, 10 pF, 200 MHz, CMOS
3.3 V option, 40 pF, 40 MHz, CMOS
Supply Current
3.3 V option, 10 pF, 200 MHz, CMOS
SSTL-3.3, 200 MHz
SSTL-2.5, 200 MHz
SSTL-1.8, 200 MHz
Output Stopped, CMOS
Tri-State
Powerdown
Output Symmetry
Times
0.5 x V
DD
CMOS, C
L
= 15 pF measured from
20 to 80% of V
DD
SSTL
CMOS Output Voltage
SSTL-1.8 Output Voltage
SSTL-2.5 Output Voltage
SSTL-3.3 Output Voltage
Powerup Time
OE Deassertion to Clk Stop
Return from Output Driver
Stopped Mode
Return from Tri-State Time
Return from Powerdown Time
Period Jitter (1-sigma)
Integrated Phase Jitter
SSTL
1 MHz – 0.4 x F
OUT
, SSTL or CMOS
and C
L
< 7 pF,
F
OUT
> 2.5 MHz
V
OH
, sourcing 9 mA
V
OL
, sinking 9 mA
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
From time V
DD
crosses min spec
supply
Min
—
—
—
—
—
—
—
—
—
—
—
—
46 – 13 ns/T
CLK
—
—
V
DD
– 0.5
—
V
TT
+ 0.375
—
V
TT
+ 0.48
—
V
TT
+ 0.48
—
—
—
—
—
—
—
—
Typ
13.9
16.7
15.8
19.3
17.7
21.5
18.1
18.0
16.8
11.8
9.7
1.0
—
1.4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
0.7
Max
16
19
18
22
20
24
20.2
19.7
18.7
13.1
10.7
1.9
54 +
13 ns/T
CLK
2.0
0.6
—
0.5
—
V
TT
– 0.375
—
V
TT
– 0.48
—
V
TT
– 0.48
2
250 +
3 x T
CLK
250 +
3 x T
CLK
12 + 3 x T
CLK
2
2
1.5
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
%
ns
ns
V
V
V
V
V
ms
ns
ns
µs
ms
ps
RMS
ps
RMS
Rise and Fall
Notes:
1.
Inclusive of 25 °C initial frequency accuracy, operating temperature range, supply voltage change, output load change,
first-year aging at 25 °C, shock, vibration, and one solder reflow.
2.
Inclusive of 25 °C initial frequency accuracy, operating temperature range, supply voltage change, output load change,
ten-year aging at 85 °C, shock, vibration, and one solder reflow.
3.
See “AN409: Output Termination Options for the Si500S and Si500D Silicon Oscillators” for further details regarding
output clock termination recommendations.
4.
V
TT
= .5 x V
DD
.
5.
V
TT
= .45 x V
DD
.
2
Rev. 1.1
SILABS [ SILICON LABORATORIES ]
