Si510/511
Table 5. Output Clock Jitter and Phase Noise (LVDS)
VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = –40 to +85 oC; Output Format = LVDS
Symbol
Test Condition
Min
Typ
Max
Unit
Parameter
1
Period Jitter
(RMS)
JPRMS
10k samples
—
—
2.1
ps
1
Period Jitter
(Pk-Pk)
JPPKPK
10k samples
—
—
—
18
ps
ps
Phase Jitter
(RMS)
φJ
1.875 MHz to 20 MHz integration
0.25
0.55
2
bandwidth (brickwall)
12 kHz to 20 MHz integration band-
—
0.8
1.0
ps
2
width (brickwall)
Phase Noise,
156.25 MHz
φN
100 Hz
1 kHz
—
—
—
—
—
—
–86
–109
–116
–123
–136
–75
—
—
—
—
—
—
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc
10 kHz
100 kHz
1 MHz
Spurious
SPR
LVPECL output, 156.25 MHz,
offset>10 kHz
Notes:
1. Applies to output frequencies: 74.17582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25,
212.5, 250 MHz.
2. Applies to output frequencies: 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 and 250 MHz.
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
7
Rev. 1.4 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • October 29, 2021
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