Si510/511
3. Pin Descriptions
VDD
1
2
4
OE
VDD
VDD
1
2
3
6
5
4
1
2
3
6
5
4
OE
NC
NC
OE
CLK–*
CLK+
CLK–*
CLK+
GND
3
CLK
GND
GND
Si510 (CMOS)
Si510 (LVDS/LVPECL/HCSL/Dual CMOS*)
Si511 (LVDS/LVPECL/HCSL/DualCMOS)*)
*Supports integrated 1:2 CMOS buffer. See ordering information and section 2.1“Dual CMOS Buffer”.
Table 11. Si510 Pin Descriptions (CMOS)
Pin
Name
CMOS Function
1
OE
Output Enable. Includes internal pull-up for OE active high. Includes
internal pull-down for OE active low. See ordering information.
2
3
4
GND
CLK
Electrical and Case Ground.
Clock Output.
V
Power Supply Voltage.
DD
Table 12. Si510 Pin Descriptions (LVPECL/LVDS/HCSL, Dual CMOS, OE Pin 2)
Pin
Name
NC
LVPECL/LVDS/HCSL Function
1
2
No connect. Make no external connection to this pin.
OE
Output Enable. Includes internal pull-up for OE active high. Includes
internal pull-down for OE active low. See ordering information.
3
4
5
6
GND
CLK+
CLK–
Electrical and Case Ground.
Clock Output.
Complementary Clock Output.
Power Supply Voltage.
V
DD
Table 13. Si511 Pin Descriptions (LVPECL/LVDS/HCSL, Dual CMOS, OE Pin 1)
Pin
Name
LVPECL/LVDS/HCSL Function
1
OE
Output Enable. Includes internal pull-up for OE active high. Includes
internal pull-down for OE active low. See ordering information.
2
3
4
5
6
NC
No connect. Make no external connection to this pin.
Electrical and Case Ground.
Clock Output.
GND
CLK+
CLK–
Complementary Clock Output.
Power Supply Voltage.
V
DD
12
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Rev. 1.4 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • October 29, 2021
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