Si510/511
Table 3. Output Clock Levels and Symmetry
VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = –40 to +85 oC
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
CMOS Output Logic
High
V
0.85 x V
—
—
V
OH
DD
CMOS Output Logic
Low
V
—
—
0.15 x V
V
OL
DD
CMOS Output Logic
High Drive
I
3.3 V
2.5 V
–8
–6
–4
8
—
—
—
—
—
—
0.8
—
—
—
—
—
—
1.2
mA
mA
mA
mA
mA
mA
ns
OH
1.8 V
CMOS Output Logic
Low Drive
I
3.3 V
OL
2.5 V
6
1.8 V
4
CMOS Output Rise/Fall T /T
Time
0.1 to 212.5 MHz,
0.45
R
F
F
C = 15 pF
L
(20 to 80% V
)
DD
0.1 to 212.5 MHz,
0.3
0.6
—
0.9
ns
ps
C = no load
L
LVPECL Output
Rise/Fall Time
(20 to 80% VDD)
T /T
100
565
R
HCSL Output Rise/Fall
Time (20 to 80% VDD)
T /T
100
350
—
—
—
470
800
—
ps
ps
V
R
F
F
LVDS Output Rise/Fall
Time (20 to 80% VDD)
T /T
R
LVPECL Output
Common Mode
V
50 to V – 2 V,
V
–
DD
1.4 V
OC
DD
single-ended
LVPECL Output Swing
V
50 to V – 2 V,
0.55
1.13
0.8
0.90
1.33
V
PPSE
O
DD
single-ended
LVDS Output Common
Mode
V
100 line-line
1.23
V
OC
V
= 3.3/2.5 V
DD
100 line-line, V = 1.8 V
0.83
0.25
0.92
0.35
1.00
0.45
V
DD
LVDS Output Swing
V
Single-ended, 100 differential
V
V
O
PPSE
termination
HCSL Output Common
Mode
V
50 to ground
0.35
0.38
0.42
V
OC
HCSL Output Swing
Duty Cycle
V
Single-ended
All formats
0.58
48
0.73
50
0.85
52
O
PPSE
DC
%
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.4 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • October 29, 2021
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