C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 15.3. XBR0: Port I/O CrossBar Register 0
R/W
R/W
R/W
Bit5
R/W
R/W
Bit3
R/W
R/W
R/W
Reset Value
CP0OEN
Bit7
ECIE
Bit6
PCA0ME
Bit4
UARTEN
Bit2
SPI0OEN
Bit1
SMB0OEN
Bit0
00000000
SFR Address:
0xE1
Bit7:
CP0OEN: Comparator 0 Output Enable Bit
0: CP0 unavailable at Port pin.
1: CP0 routed to Port Pin.
Bit6:
ECIE: PCA0 Counter Input Enable Bit
0: ECI unavailable at Port pin.
1: ECI routed to Port Pin.
Bits3-5: PCA0ME: PCA Module I/O Enable Bits
000: All PCA I/O unavailable at Port pins.
001: CEX0 routed to Port Pin.
010: CEX0, CEX1 routed to 2 Port Pins.
011: CEX0, CEX1, CEX2 routed to 3 Port Pins.
100: CEX0, CEX1, CEX2, CEX3 routed to 4 Port Pins.
101: CEX0, CEX1, CEX2, CEX3, CEX4 routed to 5 Port Pins.
110: RESERVED
111: RESERVED
Bit2:
UARTEN: UART I/O Enable Bit
0: UART I/O unavailable at Port pins.
1: RX, TX routed to 2 Port Pins.
Bit1:
SPI0OEN: SPI Bus I/O Enable Bit
0: SPI I/O unavailable at Port pins.
1: MISO, MOSI, SCK, and NSS routed to 4 Port Pins.
Bit0:
SMB0OEN: SMBus Bus I/O Enable Bit
0: SMBus I/O unavailable at P0.0, P0.1.
1: SDA routed to P0.0, SCL routed to P0.1.
Rev. 1.7
106
SILABS [ SILICON LABORATORIES ]
