C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
16.6.2. Clock Rate Register
Figure 16.5. SMB0CR: SMBus Clock Rate Register
R/W
Bit7
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W
Bit0
Reset Value
00000000
SFR Address:
0xCF
Bits7-0: SMB0CR.[7:0]: SMBus Clock Rate Preset
The SMB0CR Clock Rate register controls the frequency of the serial clock SCL in master
mode. The 8-bit word stored in the SMB0CR Register preloads a dedicated 8-bit timer.
The timer counts up, and when it rolls over to 0x00, the SCL logic state toggles.
The SMB0CR setting should be bounded by the following equation, where
SMB0CR
is the
unsigned 8-bit value in register SMB0CR, and
SYSCLK
is the system clock frequency in
Hz:
SMB0CR < ((288 - 0.85 * SYSCLK) / 1.125
E
6)
The resulting SCL signal high and low times are given by the following equations:
T
LOW
= (256 – SMB0CR) / SYSCLK
T
HIGH
≅
(258 – SMB0CR) / SYSCLK + 625 ns
Using the same value of SMB0CR from above, the Bus Free Timeout period is given in the
following equation:
T
BFT
≅
10 * [(256 – SMB0CR) + 1] / SYSCLK
119
Rev. 1.7
SILABS [ SILICON LABORATORIES ]
