C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
18. UART
The UART is a serial port capable of asynchronous transmission. The UART can function in full duplex mode. In
all modes, receive data is buffered in a holding register. This allows the UART to start reception of a second
incoming data byte before software has finished reading the previous data byte.
The UART has an associated Serial Control Register (SCON) and a Serial Data Buffer (SBUF) in the SFRs. The
single SBUF location provides access to both transmit and receive registers. Reads access the Receive register and
writes access the Transmit register automatically.
The UART is capable of generating interrupts if enabled. The UART has two sources of interrupts: a Transmit
Interrupt flag, TI (SCON.1) set when transmission of a data byte is complete, and a Receive Interrupt flag, RI
(SCON.0) set when reception of a data byte is complete. The UART interrupt flags are not cleared by hardware
when the CPU vectors to the interrupt service routine. They must be cleared manually by software. This allows
software to determine the cause of the UART interrupt (transmit complete or receive complete).
Figure 18.1. UART Block Diagram
SFR Bus
PCON
S
M
O
D
Write to
SBUF
TB8
SCON
S S S R T R T R
M M M E B B I I
0 1 2 N 8 8
T2CON
R
C
L
K
T
C
L
K
SET
D
CLR
Q
SBUF
TX
Crossbar
Zero Detector
Baud Rate Generation Logic
Start
Timer 1
Overflow
1
0
0
1
SMOD
TCLK
SM0, SM1
{MODE}
0
Timer 2
Overflow
00
00
01
10
11
Serial
Port
Interrupt
RI
Rx Clock
Rx IRQ
Enable
MSB
Load
SBUF
Shift
0x1FF
Tx Clock
TI
Stop Bit
Gen.
Shift
Data
2
Tx Control
Tx IRQ
Send
16
REN
RB8
16
1
RCLK
01
10
11
Rx Control
Start
32
64
SYSCLK
1
0
Port I/O
Bit Detector
Input Shift Register
(9 bits)
Shift
Load SBUF
SMOD
12
SBUF
Read
SBUF
SFR Bus
RX
Crossbar
Rev. 1.7
130
SILABS [ SILICON LABORATORIES ]
