C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
5.3.
ADC Programmable Window Detector
The ADC programmable window detector is very useful in many applications. It continuously compares the ADC
output to user-programmed limits and notifies the system when an out-of-band condition is detected. This is
especially effective in an interrupt-driven system, saving code space and CPU bandwidth while delivering faster
system response times. The window detector interrupt flag (ADWINT in ADC0CN) can also be used in polled
mode. The high and low bytes of the reference words are loaded into the ADC Greater-Than and ADC Less-Than
registers (ADC0GTH, ADC0GTL, ADC0LTH, and ADC0LTL). Figure 5.14 and Figure 5.15 show example
comparisons for reference. Notice that the window detector flag can be asserted when the measured data is inside
or outside the user-programmed limits, depending on the programming of the ADC0GTx and ADC0LTx registers.
Figure 5.10. ADC0GTH: ADC Greater-Than Data High Byte Register (C8051F00x)
R/W
Bit7
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W
Bit0
Reset Value
11111111
SFR Address:
Bits7-0:
The high byte of the ADC Greater-Than Data Word.
0xC5
Figure 5.11. ADC0GTL: ADC Greater-Than Data Low Byte Register (C8051F00x)
R/W
Bit7
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W
Bit0
Reset Value
11111111
SFR Address:
0xC4
Bits7-0:
The low byte of the ADC Greater-Than Data Word.
Definition:
ADC Greater-Than Data Word = ADC0GTH:ADC0GTL
Figure 5.12. ADC0LTH: ADC Less-Than Data High Byte Register (C8051F00x)
R/W
Bit7
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W
Bit0
Reset Value
00000000
SFR Address:
0xC7
Bits7-0:
The high byte of the ADC Less-Than Data Word.
Figure 5.13. ADC0LTL: ADC Less-Than Data Low Byte Register (C8051F00x)
R/W
Bit7
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W
Bit0
Reset Value
00000000
SFR Address:
0xC6
Bits7-0:
These bits are the low byte of the ADC Less-Than Data Word.
Definition:
ADC Less-Than Data Word = ADC0LTH:ADC0LTL
Rev. 1.7
36