C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Table 13.1. Reset Electrical Characteristics
-40°C to +85°C unless otherwise specified.
PARAMETER
CONDITIONS
/RST Output Low Voltage
I
OL
= 8.5mA, VDD = 2.7 to 3.6V
/RST Input High Voltage
/RST Input Low Voltage
/RST Input Leakage Current
VDD for /RST Output Valid
AV+ for /RST Output Valid
VDD POR Threshold (V
RST
)
Reset Time Delay
Missing Clock Detector
Timeout
/RST = 0.0V
1.0
1.0
2.40
80
100
20
MIN
0.7 x
VDD
0.3 x
VDD
TYP
MAX
0.6
UNITS
V
V
V
µA
V
V
V
ms
µs
/RST rising edge after crossing reset
threshold
Time from last system clock to reset
generation
2.55
100
220
2.70
120
500
Rev. 1.7
98