C8051F132
100 MIPS, 64 kB Flash, 10-Bit ADC, 100-Pin Mixed-Signal MCU
Analog Peripherals
10-Bit ADC
High-Speed 8051 µC Core
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
±1 LSB INL; no missing codes
Programmable throughput up to 100 ksps
8 external inputs; programmable as single-ended or differential
Programmable amplifier gain: 16, 8, 4, 2, 1, 0.5
Data-dependent windowed interrupt generator
Built-in temperature sensor (±3 °C)
Pipelined instruction architecture; executes 70% of instructions in 1 or 2
system clocks
Up to 100 MIPS throughput with 100 MHz system clock
16 x 16 multiply/accumulate engine (2-cycle)
8448 bytes data RAM
64 kB Flash; in-system programmable in 1024-byte sectors (1024 bytes
are reserved)
External parallel data memory interface
64 port I/O; all are 5 V tolerant
Hardware SMBus™ (I2C™ compatible), SPI™, and two UART serial
ports available concurrently
Programmable 16-bit counter/timer array with six capture/compare
modules
5 general-purpose 16-bit counter/timers
Dedicated watchdog timer; bidirectional reset
Real-time clock mode using timer 3 or PCA
Internal oscillator: 24.5 MHz, 2% accuracy supports UART operation
On-chip programmable PLL: up to 100 MHz
External oscillator: Crystal, RC, C, or Clock
Typical operating current: 50 mA at 100 MHz
Typical stop mode current: 0.4 µA
Memory
Two Comparators
Internal Voltage Reference
V
DD
Monitor/Brown-out Detector
On-Chip JTAG Debug & Boundary Scan
Digital Peripherals
-
-
-
-
-
On-chip debug circuitry facilitates full speed, non-intrusive in-system
debug (no emulator required)
Provides breakpoints, single stepping, watchpoints, stack monitor
Inspect/modify memory and registers
Superior performance to emulation systems using ICE-chips, target
pods, and sockets
IEEE1149.1 compliant boundary scan
Clock Sources
Supply Voltage: 3.0 to 3.6 V
100-Pin TQFP
Temperature Range: –40 to +85 °C
VDD
VDD
VDD
DGND
DGND
DGND
AV+
AV+
AGND
AGND
TCK
TMS
TDI
TDO
RST
Digital Power
Port I/O
Config.
UART0
P0
Drv
P0.0
P0.7
SFR Bus
Analog Power
UART1
SMBus
JTAG
Logic
Boundary Scan
Debug HW
Reset
MONEN
VDD
Monitor
WDT
8
0
5
1
C
o
r
e
256 byte
RAM
8kbyte
XRAM
External Data
Memory Bus
SPI Bus
PCA
Timers 0,
1, 2, 4
Timer 3/
RTC
P0, P1,
P2, P3
Latches
Crossbar
Config.
C
R
O
S
S
B
A
R
P1
Drv
P1.0/AIN2.0
P1.7/AIN2.7
P2
Drv
P2.0
P2.7
P3
Drv
P3.0
P3.7
XTAL1
XTAL2
External Oscillator
Circuit
PLL
Circuitry
Calibrated Internal
Oscillator
System
Clock
VREF
VREF
FLASH
64kbyte
P4.0
Bus Control
VREF0
AIN0.0
AIN0.1
AIN0.2
AIN0.3
AIN0.4
AIN0.5
AIN0.6
AIN0.7
CP0+
CP0-
CP1+
CP1-
64x4 byte
cache
A
M
U
X
C
T
L
P4 Latch
P4
DRV
P4.4
P4.5/ALE
P4.6/RD
P4.7/WR
P5.0/A8
P5.7/A15
P6.0/A0
P6.7/A7
Prog
Gain
ADC
100ksps
(10-Bit)
Address Bus
A
d
d
r
D
a
t
a
P5 Latch
P6 Latch
P5
DRV
P6
DRV
TEMP
SENSOR
Data Bus
P7 Latch
CP0
CP1
P7
DRV
P7.0/D0
P7.7/D7
General Purpose
Copyright © 2004 by Silicon Laboratories
8.9.2004
SILABS [ SILICON LABORATORIES ]
