C8051F020/1/2/3
23.2.1. Edge-triggered Capture Mode
In this mode, a valid transition on the CEXn pin causes PCA0 to capture the value of the PCA0 counter/timer and
load it into the corresponding module's 16-bit capture/compare register (PCA0CPLn and PCA0CPHn). The CAPPn
and CAPNn bits in the PCA0CPMn register are used to select the type of transition that triggers the capture: low-to-
high transition (positive edge), high-to-low transition (negative edge), or either transition (positive or negative edge).
When a capture occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to logic 1 and an interrupt request is
generated if CCF interrupts are enabled. The CCFn bit is not automatically cleared by hardware when the CPU vec-
tors to the interrupt service routine, and must be cleared by software.
Figure 23.4. PCA Capture Mode Diagram
PCA Interrupt
PCA0CPMn
P
ECCMT
P
E
W
C A A AO
W
C
M
OPP TG
M
C
1
MP N n n
n
F
6
n n n
n
n
PCA0CN
CC
FR
CCCCC
CCCCC
FFFFF
4 3 2 1 0
(to CCFn)
PCA0CPLn
PCA0CPHn
0
Port I/O
Crossbar
CEXn
1
0
1
PCA
Timebase
Capture
PCA0L
PCA0H
Note: The CEXn input signal must remain high or low for at least 2 system clock cycles in order to be valid.
Rev. 1.4
253
SILABS [ SILICON LABORATORIES ]
