C8051F020/1/2/3
24.
JTAG (IEEE 1149.1)
Each MCU has an on-chip JTAG interface and logic to support boundary scan for production and in-system testing,
Flash read/write operations, and non-intrusive in-circuit debug. The JTAG interface is fully compliant with the IEEE
1149.1 specification. Refer to this specification for detailed descriptions of the Test Interface and Boundary-Scan
Architecture. Access of the JTAG Instruction Register (IR) and Data Registers (DR) are as described in the Test
Access Port and Operation of the IEEE 1149.1 specification.
The JTAG interface is accessed via four dedicated pins on the MCU: TCK, TMS, TDI, and TDO.
Through the 16-bit JTAG Instruction Register (IR), any of the seven instructions shown in Figure 24.1 can be com-
manded. There are three DR’s associated with JTAG Boundary-Scan, and four associated with Flash read/write oper-
ations on the MCU.
Figure 24.1. IR: JTAG Instruction Register
Reset Value
0x0000
Bit15
Bit0
IR Value
0x0000
0x0002
0x0004
0xFFFF
0x0082
0x0083
0x0084
Instruction
EXTEST
SAMPLE/
PRELOAD
IDCODE
BYPASS
Flash Control
Flash Data
Flash Address
Description
Selects the Boundary Data Register for control and observability of all device pins
Selects the Boundary Data Register for observability and presetting the scan-path
latches
Selects device ID Register
Selects Bypass Data Register
Selects FLASHCON Register to control how the interface logic responds to reads
and writes to the FLASHDAT Register
Selects FLASHDAT Register for reads and writes to the Flash memory
Selects FLASHADR Register which holds the address of all Flash read, write, and
erase operations
Rev. 1.4
265
SILABS [ SILICON LABORATORIES ]
