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STK10C68-5S35M 参数 Datasheet PDF下载

STK10C68-5S35M图片预览
型号: STK10C68-5S35M
PDF下载: 下载PDF文件 查看货源
内容描述: 8K ×8的nvSRAM QuantumTrap⑩ CMOS非易失性静态RAM [8K x 8 nvSRAM QuantumTrap⑩ CMOS Nonvolatile Static RAM]
分类和应用: 存储内存集成电路静态存储器光电二极管
文件页数/大小: 12 页 / 471 K
品牌: SIMTEK [ SIMTEK CORPORATION ]
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STK10C68  
STK10C68-M SMD#5962-93056  
8K x 8 nvSRAM  
QuantumTrap™ CMOS  
Nonvolatile Static RAM  
Obsolete - Not Recommend for new Designs  
DESCRIPTION  
FEATURES  
The Simtek STK10C68 is a fast static RAM with a nonvol-  
atile element incorporated in each static memory cell. The  
SRAM can be read and written an unlimited number of  
times, while independent nonvolatile data resides in Non-  
volatile Elements. Data may easily be transferred from  
the SRAM to the Nonvolatile Elements (the STORE oper-  
ation), or from the Nonvolatile Elements to the SRAM  
(the RECALL operation), using the NE pin. Transfers  
from the Nonvolatile Elements to the SRAM (the  
RECALL operation) also take place automatically on  
restoration of power. The STK10C68 combines the high  
performance and ease of use of a fast SRAM with nonvol-  
atile data integrity.  
• 25ns, 35ns, 45ns and 55ns Access Times  
STORE to Nonvolatile Elements Initiated by  
Hardware  
RECALL to SRAM Initiated by Hardware or  
Power Restore  
• Automatic STORE Timing  
• 10mA Typical ICC at 200ns Cycle Time  
• Unlimited READ, WRITE and RECALL Cycles  
• 1,000,000 STORE Cycles to Nonvolatile Ele-  
ments (Industrial/Commercial)  
• 100-Year Data Retention (Industrial/Commer-  
cial)  
• Commercial, Industrial and Military Tempera-  
tures  
• 28-Pin DIP, SOIC and LCC Packages  
The STK10C68 features industry-standard pinout for non-  
volatile RAMs. MIL-STD-883 and Standard Military Draw-  
ing (SMD #5962-93056) devices are available.  
PIN CONFIGURATIONS  
BLOCK DIAGRAM  
1
NE  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
V
CC  
W
NC  
2
A
QUANTUM TRAP  
128 x 512  
12  
3
A
A
A
A
A
A
A
A
DQ  
7
6
5
4
3
2
4
A
8
5
A
A
G
9
A
5
6
11  
STORE  
7
A
A
A
A
A
A
6
8
A
E
10  
9
1
0
7
STATIC RAM  
ARRAY  
10  
11  
12  
13  
14  
DQ  
DQ  
DQ  
7
RECALL  
0
6
5
8
DQ  
DQ  
1
128 x 512  
DQ  
DQ  
2
4
3
9
V
SS  
11  
12  
28 - DIP  
28 - SOIC  
28 - LCC  
DQ0  
DQ1  
DQ2  
DQ3  
DQ4  
DQ5  
DQ6  
DQ7  
COLUMN I/O  
STORE/  
RECALL  
CONTROL  
PIN NAMES  
COLUMN DEC  
A
- A  
12  
Address Inputs  
Write Enable  
Data In/Out  
0
W
A3 A  
4 A10  
A0 A1 A2  
DQ - DQ  
0
7
G
NE  
E
Chip Enable  
Output Enable  
Nonvolatile Enable  
Power (+ 5V)  
Ground  
G
E
NE  
W
V
CC  
SS  
V
March 2006  
1
Document Control # ML0006 rev 0.2