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STK11C68-5C25M 参数 Datasheet PDF下载

STK11C68-5C25M图片预览
型号: STK11C68-5C25M
PDF下载: 下载PDF文件 查看货源
内容描述: [Non-Volatile SRAM, 8KX8, 25ns, CMOS, CDIP28, 0.300 INCH, CERAMIC, DIP-28]
分类和应用: 静态存储器内存集成电路
文件页数/大小: 10 页 / 314 K
品牌: SIMTEK [ SIMTEK CORPORATION ]
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STK11C68  
STK11C68-M SMD#5962-92324  
8K x 8 nvSRAM  
QuantumTrap™ CMOS  
Nonvolatile Static RAM  
FEATURES  
DESCRIPTION  
• 25ns, 35ns, 45ns and 55ns Access Times  
The Simtek STK11C68 is a fast static RAM with a  
nonvolatile element incorporated in each static  
memory cell. The SRAM can be read and written an  
unlimited number of times, while independent non-  
volatile data resides in the Nonvolatile Elements.  
Data transfers from the SRAM to the Nonvolatile Ele-  
ments (the STORE operation), or from Nonvolatile  
Elements to SRAM (the RECALL operation), take  
place using a software sequence. Transfers from the  
Nonvolatile Elements to the SRAM (the RECALL  
operation) also take place automatically on restora-  
tion of power.  
STORE to Nonvolatile Elements Initiated by  
Software  
RECALL to SRAM Initiated by Software or  
Power Restore  
• 10mA Typical ICC at 200ns Cycle Time  
• Unlimited READ, WRITE and RECALL Cycles  
• 1,000,000 STORE Cycles to Nonvolatile Ele-  
ments (Industrial/Commercial)  
• 100-Year Data Retention (Industrial/Commer-  
cial)  
• Commercial, Industrial and Military Tempera-  
tures  
• 28-Pin DIP, SOIC and LCC Packages  
The STK11C68 is pin-compatible with industry-  
standard SRAMs. MIL-STD-883 device is also  
available (STK11C68-M).  
BLOCK DIAGRAM  
PIN CONFIGURATIONS  
NC  
A12  
A7  
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
VCC  
W
QUANTUM TRAP  
128 x 512  
2
3
4
5
6
7
8
9
NC  
A8  
A6  
A5  
A6  
A5  
A9  
STORE  
A4  
A11  
G
A10  
E
STORE/  
RECALL  
A3  
A7  
A8  
A9  
A2  
STATIC RAM  
ARRAY  
CONTROL  
A1  
RECALL  
10  
11  
12  
13  
14  
A0  
DQ7  
DQ6  
DQ5  
DQ4  
DQ3  
128 x 512  
DQ0  
DQ1  
DQ2  
VSS  
A11  
A12  
SOFTWARE  
DETECT  
A
- A  
12  
0
28 - LCC  
28 - DIP  
28 - SOIC  
DQ  
DQ  
DQ  
0
1
2
COLUMN I/O  
PIN NAMES  
COLUMN DEC  
DQ  
A
- A  
Address Inputs  
Write Enable  
Data In/Out  
Chip Enable  
Output Enable  
Power (+ 5V)  
Ground  
3
4
0
12  
DQ  
W
DQ  
DQ  
DQ  
5
6
7
A
A A  
A A  
1 4  
2 3  
A
0
10  
G
DQ - DQ  
0
7
E
E
W
G
V
V
CC  
SS  
September 2003  
1
Document Control # ML0007 rev 0.1