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STK11C88-3S45 参数 Datasheet PDF下载

STK11C88-3S45图片预览
型号: STK11C88-3S45
PDF下载: 下载PDF文件 查看货源
内容描述: 32K ×8的nvSRAM 3.3V QuantumTrap⑩ CMOS非易失性静态RAM [32K x 8 nvSRAM 3.3V QuantumTrap⑩ CMOS Nonvolatile Static RAM]
分类和应用: 静态存储器
文件页数/大小: 10 页 / 369 K
品牌: SIMTEK [ SIMTEK CORPORATION ]
 浏览型号STK11C88-3S45的Datasheet PDF文件第2页浏览型号STK11C88-3S45的Datasheet PDF文件第3页浏览型号STK11C88-3S45的Datasheet PDF文件第4页浏览型号STK11C88-3S45的Datasheet PDF文件第5页浏览型号STK11C88-3S45的Datasheet PDF文件第6页浏览型号STK11C88-3S45的Datasheet PDF文件第7页浏览型号STK11C88-3S45的Datasheet PDF文件第8页浏览型号STK11C88-3S45的Datasheet PDF文件第9页  
STK11C88-3  
32K x 8 nvSRAM  
3.3V QuantumTrap™ CMOS  
Nonvolatile Static RAM  
Obsolete - Not Recommend for new Deisgns  
FEATURES  
DESCRIPTION  
• 35, 45ns and 55ns Access Times  
The Simtek STK11C88-3 is a fast static RAM with a  
nonvolatile element incorporated in each static  
memory cell. The SRAM can be read and written an  
unlimited number of times, while independent non-  
volatile data resides in Nonvolatile Elements. Data  
transfers from the SRAM to the Nonvolatile Elements  
(the STORE operation), or from Nonvolatile Elements  
to SRAM (the RECALL operation) are initiated using a  
software sequence. Data transfers from the Nonvol-  
atile Elements to the SRAM (the RECALL operation)  
also occur upon restoration of power.  
STORE to Nonvolatile Elements Initiated by  
Software  
RECALL to SRAM Initiated by Software or  
Power Restore  
• 10 mA Typical Icc at 200 nsec Cycle Time  
• Unlimited READ, WRITE and RECALL Cycles  
• 1,000,000 STORE Cycles to Nonvolatile Ele-  
ments  
• 100-Year Data Retention in Nonvolatile Ele-  
ments  
• Single 3.3V+ 0.3V Operation  
• Commercial and Industrial Temperatures  
• 28-Pin DIP and SOIC Packages  
BLOCK DIAGRAM  
PIN CONFIGURATIONS  
1
A
A
A
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
V
CC  
W
14  
QUANTUM TRAP  
2
12  
512 x 512  
3
A
A
A
A
7
6
5
4
3
2
13  
8
A5  
A6  
A7  
A8  
4
A
5
A
A
A
A
A
A
DQ  
DQ  
DQ  
9
STORE  
6
STORE/  
RECALL  
CONTROL  
11  
7
G
STATIC RAM  
ARRAY  
8
A
E
10  
RECALL  
A9  
9
1
A11  
A12  
A13  
A14  
512 x 512  
10  
11  
12  
13  
14  
DQ  
DQ  
0
7
6
5
28 - 300 PDIP  
28 - 600 PDIP  
28 - 300 SOIC  
28 - 350 SOIC  
0
DQ  
1
2
DQ  
DQ  
4
3
SOFTWARE  
DETECT  
A0 - A13  
V
SS  
DQ0  
DQ1  
DQ2  
DQ3  
DQ4  
DQ5  
DQ6  
DQ7  
PIN NAMES  
COLUMN I/O  
A
- A  
Address Inputs  
Write Enable  
Data In/Out  
COLUMN DEC  
0
14  
W
DQ - DQ  
0
7
A
A0 A1 A2 A3 A4  
10  
G
E
Chip Enable  
Output Enable  
Power (+ 3.3V)  
Ground  
G
E
V
V
CC  
SS  
W
March 2006  
1
Document Control # ML0013 rev 0.2