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STK11C88-WF35I 参数 Datasheet PDF下载

STK11C88-WF35I图片预览
型号: STK11C88-WF35I
PDF下载: 下载PDF文件 查看货源
内容描述: [Non-Volatile SRAM, 32KX8, 35ns, CMOS, PDIP28, 0.600 INCH, PLASTIC, DIP-28]
分类和应用: 静态存储器光电二极管内存集成电路
文件页数/大小: 10 页 / 285 K
品牌: SIMTEK [ SIMTEK CORPORATION ]
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STK11C88  
32K x 8 nvSRAM  
QuantumTrap™ CMOS  
Nonvolatile Static RAM  
FEATURES  
DESCRIPTION  
• 25ns, 35ns and 45ns Access Times  
The Simtek STK11C88 is a fast static RAM with a  
nonvolatile element incorporated in each static  
memory cell. The SRAM can be read and written an  
unlimited number of times, while independent non-  
volatile data resides in Nonvolatile Elements. Data  
transfers from the SRAM to the Nonvolatile Elements  
(the STORE operation), or from Nonvolatile Elements  
to SRAM (the RECALL operation), are initiated using  
a software sequence. Data transfers from the Non-  
volatile Elements to the SRAM (the RECALL opera-  
tion) also occur upon restoration of power.  
STORE to Nonvolatile Elements Initiated by  
Software  
RECALL to SRAM Initiated by Software or  
Power Restore  
• 10mA Typical ICC at 200ns Cycle Time  
• Unlimited READ, WRITE and RECALL Cycles  
• 1,000,000 STORE Cycles to Nonvolatile Ele-  
ments (Commercial/Industrial)  
• 100-Year Data Retention in Nonvolatile Ele-  
ments (Commercial/Industrial)  
The STK11C88 is pin-compatible with industry-  
standard SRAMs.  
• Single 5V + 10% Operation  
• Commercial and Industrial Temperatures  
• 28-Pin PDIP and SOIC Packages  
BLOCK DIAGRAM  
PIN CONFIGURATIONS  
A14  
A12  
A7  
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
VCC  
W
QUANTUM TRAP  
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
512 x 512  
A13  
A8  
A5  
A6  
A5  
A9  
A6  
STORE  
STORE/  
RECALL  
A4  
A11  
G
A10  
E
DQ7  
DQ6  
DQ5  
DQ4  
DQ3  
A7  
A3  
A8  
STATIC RAM  
ARRAY  
A2  
CONTROL  
RECALL  
A9  
A1  
A11  
A12  
A13  
A14  
512 x 512  
A0  
28 - 300 PDIP  
28 - 600 PDIP  
28 - 300 SOIC  
28 - 350 SOIC  
DQ0  
DQ1  
DQ2  
VSS  
SOFTWARE  
DETECT  
A
- A  
13  
0
DQ  
DQ  
DQ  
0
1
2
COLUMN I/O  
PIN NAMES  
COLUMN DEC  
A
- A  
Address Inputs  
Write Enable  
Data In/Out  
Chip Enable  
Output Enable  
Power (+5V)  
Ground  
0
14  
DQ  
3
4
DQ  
W
DQ  
DQ  
DQ  
5
6
7
A
0
A A A  
A A  
1 4  
2 3  
10  
DQ - DQ  
0
7
G
E
E
W
G
V
V
CC  
SS  
September 2003  
1
Document Control # ML0012 rev 0.1