欢迎访问ic37.com |
会员登录 免费注册
发布采购

STK14C88-N45 参数 Datasheet PDF下载

STK14C88-N45图片预览
型号: STK14C88-N45
PDF下载: 下载PDF文件 查看货源
内容描述: [Non-Volatile SRAM, 32KX8, 45ns, CMOS, PDSO32, 0.300 INCH, PLASTIC, SOIC-32]
分类和应用: 可编程只读存储器电动程控只读存储器电可擦编程只读存储器静态存储器光电二极管内存集成电路
文件页数/大小: 12 页 / 120 K
品牌: SIMTEK [ SIMTEK CORPORATION ]
 浏览型号STK14C88-N45的Datasheet PDF文件第2页浏览型号STK14C88-N45的Datasheet PDF文件第3页浏览型号STK14C88-N45的Datasheet PDF文件第4页浏览型号STK14C88-N45的Datasheet PDF文件第5页浏览型号STK14C88-N45的Datasheet PDF文件第6页浏览型号STK14C88-N45的Datasheet PDF文件第7页浏览型号STK14C88-N45的Datasheet PDF文件第8页浏览型号STK14C88-N45的Datasheet PDF文件第9页  
STK14C88  
32K x 8 AutoStore™ nvSRAM  
QuantumTrap™ CMOS  
Nonvolatile Static RAM  
FEATURES  
DESCRIPTION  
20ns, 25ns, 35ns and 45ns Access Times  
The Simtek STK14C88 is a fast static RAM with a  
• “Hands-offAutomatic STORE with External  
68µF Capacitor on Power Down  
nonvolatile, electrically erasable PROM element  
incorporated in each static memory cell. The SRAM  
can be read and written an unlimited number of  
times, while independent, nonvolatile data resides in  
EEPROM. Data transfers from the SRAM to the  
EEPROM (the STORE operation) can take place  
automatically on power down. A 68µF or larger  
capacitor tied from VCAP to ground guarantees the  
STORE operation, regardless of power-down slew  
rate or loss of power from “hot swapping”. Transfers  
from the EEPROM to the SRAM (the RECALL opera-  
tion) take place automatically on restoration of  
power. Initiation of STORE and RECALL cycles can  
also be software controlled by entering specific read  
sequences. A hardware STORE may be initiated with  
the HSB pin.  
STORE to EEPROM Initiated by Hardware,  
Software or AutoStoreon Power Down  
RECALL to SRAM Initiated by Software or  
Power Restore  
10mA Typical ICC at 200ns Cycle Time  
Unlimited READ, WRITE and RECALL Cycles  
1,000,000 STORE Cycles to EEPROM  
100-Year Data Retention in EEPROM  
Single 5V + 10% Operation  
Not Sensitive to Power On/Off Ramp Rates  
No Data Loss from Undershoot  
Commercial and Industrial Temperatures  
32-Pin SOIC and DIP Packages  
BLOCK DIAGRAM  
PIN CONFIGURATIONS  
V
V
1
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
CCX  
CAP  
VCCX  
VCAP  
A
2
HSB  
W
14  
A
3
12  
A
A
A
A
A
NC  
A
2
A
A
4
A
7
6
5
4
3
13  
EEPROM ARRAY  
512 x 512  
5
A
8
POWER  
CONTROL  
A
9
A
11  
G
NC  
6
A5  
A6  
A7  
7
8
STORE  
9
10  
11  
12  
13  
14  
15  
16  
A
STORE/  
RECALL  
CONTROL  
10  
A8  
STATIC RAM  
E
1
HSB  
RECALL  
A9  
ARRAY  
DQ  
0
7
6
5
512 x 512  
A11  
A12  
A13  
A14  
DQ  
DQ  
DQ  
DQ  
DQ  
0
1
2
32 - 300 SOIC  
32 - 600 PDIP  
DQ  
DQ  
4
3
V
SS  
SOFTWARE  
DETECT  
A0 - A13  
DQ0  
DQ1  
DQ2  
PIN NAMES  
COLUMN I/O  
A - A  
Address Inputs  
COLUMN DEC  
0
14  
DQ -DQ  
0
Data In/Out  
DQ3  
DQ4  
7
E
Chip Enable  
DQ5  
DQ6  
DQ7  
W
Write Enable  
Output Enable  
Hardware Store Busy (I/O)  
Power (+ 5V)  
Capacitor  
A0 A1 A2 A3 A4 A10  
G
G
HSB  
E
V
V
V
CCX  
CAP  
SS  
W
Ground  
July 1999  
5-21