STK15C88-3
32K x 8
AutoStore™
nvSRAM
3.3V QuantumTrap™
CMOS
Nonvolatile Static RAM
FEATURES
• Nonvolatile Storage without Battery Problems
• Directly Replaces 32K x 8 Static RAM, Battery-
Backed RAM or EEPROM
• 35ns, 45ns and 55ns Access Times
•
STORE
to EEPROM Initiated by Software or
AutoStore™
on Power Down
•
RECALL
to SRAM Initiated by Software or
Power Restore
• 8mA Typical I
CC
at 200ns Cycle Time
• Unlimited READ, WRITE and
RECALL
Cycles
• 1,000,000
STORE
Cycles to EEPROM
• 100-Year Data Retention over Full Industrial
Temperature Range
• 3.0V-3.6V Operation
• Commercial and Industrial Temperatures
• 28-Pin PDIP and SOIC Packages
DESCRIPTION
The STK15C88-3 is a fast
SRAM
with a nonvolatile
EEPROM
element incorporated in each static mem-
ory cell. The
SRAM
can be read and written an
unlimited number of times, while independent non-
volatile data resides in
EEPROM
. Data transfers from
the
SRAM
to the
EEPROM
(the
STORE
operation) can
take place automatically on power down using
charge stored in system capacitance. Transfers
from the
EEPROM
to the
SRAM
(the
RECALL
opera-
tion) take place automatically on restoration of
power. Initiation of
STORE
and
RECALL
cycles can
also be controlled by entering control sequences on
the
SRAM
inputs. The STK15C88-3 is pin-compati-
ble with 32k x 8
SRAM
s and battery-backed
SRAM
s,
allowing direct substitution while enhancing perfor-
mance. A similar device (STK16C88-3) with an
internally integrated capacitor is available for appli-
cations with very fast power-down slew rates. The
STK14C88-3, which uses an external capacitor, is
another alternative for these applications.
BLOCK DIAGRAM
EEPROM ARRAY
512 x 512
PIN CONFIGURATIONS
V
CC
STORE/
RECALL
CONTROL
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ
0
DQ
1
DQ
2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A
5
A
6
A
7
A
8
A
9
A
11
A
12
A
13
A
14
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
ROW DECODER
STORE
STATIC RAM
ARRAY
512 x 512
RECALL
POWER
CONTROL
SOFTWARE
DETECT
INPUT BUFFERS
COLUMN I/O
COLUMN DEC
A
0
- A
13
V
CC
W
A
13
A
8
A
9
A
11
G
A
10
E
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
28 - 300 PDIP
28 - 600 PDIP
28 - 300 SOIC
28 - 350 SOIC
PIN NAMES
A
0
- A
14
W
Address Inputs
Write Enable
Data In/Out
Chip Enable
Output Enable
Power (+ 5V)
Ground
A
0
A
1
A
2
A
3
A
4
A
10
DQ
0
- DQ
7
G
E
W
E
G
V
CC
V
SS
September 2002
1