P r e l i m i n a r y
Command Definitions
Table 31. Command Definitions (x16 Mode, BYTE# = VIH
)
Bus Cycles (Notes 2–5)
Command
Sequence
(Note 1)
First
Second
Third
Fourth
Addr Data
Fifth
Sixth
Addr Data
Addr
Data
Addr
Data
Addr Data Addr Data
Read (Note 6)
Reset (Note 7)
1
1
RA
XXX
555
RD
F0
Manufacturer ID
4
AA
2AA
2AA
55
55
555
555
90
90
X00
X01
0001
227E
(Note
18)
(Note
18)
Device ID (Note 9)
4
4
4
555
555
555
AA
AA
AA
X0E
X0F
SecSi‰ Sector Factory Protect
(Note 10)
2AA
2AA
55
55
555
555
90
90
X03
(Note 10)
00/01
Sector Group Protect Verify (Note
12)
(SA)X02
Enter SecSi Sector Region
Exit SecSi Sector Region
Program
3
4
4
3
1
555
555
AA
AA
AA
AA
29
2AA
2AA
2AA
2AA
55
55
55
55
555
555
555
SA
88
90
A0
25
XXX
PA
00
PD
555
Write to Buffer (Note 11)
Program Buffer to Flash
Write to Buffer Abort Reset (Note 13)
Unlock Bypass
555
SA
WC
PA
PD
WBL
PD
SA
3
3
2
2
6
6
1
555
AA
AA
A0
90
2AA
2AA
PA
55
55
555
555
F0
20
555
Unlock Bypass Program (Note 14)
Unlock Bypass Reset (Note 15)
Chip Erase
XXX
XXX
555
PD
00
55
XXX
2AA
2AA
AA
AA
B0
555
555
80
80
555
555
AA
AA
2AA
2AA
55
55
555
SA
10
Sector Erase
555
55
30
Program/Erase Suspend (Note 16)
Program/Erase Resume (Note 17)
CFI Query (Note 18)
XXX
XXX
55
1
30
1
98
Legend:
X = Don’t care
RA = Read Address of memory location to be read.
PD = Program Data for location PA. Data latches on rising edge of
WE# or CE# pulse, whichever happens first.
SA = Sector Address of sector to be verified (in autoselect mode) or
erased. Address bits A21–A15 uniquely select any sector.
WBL = Write Buffer Location. Address must be within same write
buffer page as PA.
RD = Read Data read from location RA during read operation.
PA = Program Address. Addresses latch on falling edge of WE# or
CE# pulse, whichever happens later.
WC = Word Count. Number of write buffer locations to load minus 1.
Notes:
1. See Table 1 for description of bus operations.
10. Data is 00h for an unprotected sector group and 01h for a
protected sector group.
2. All values are in hexadecimal.
11. Total number of cycles in command sequence is determined by
number of words written to write buffer. Maximum number of
cycles in command sequence is 21, including “Program Buffer to
Flash” command.
12. Command sequence resets device for next command after
aborted write-to-buffer operation.
13. Unlock Bypass command is required prior to Unlock Bypass
Program command.
14. Unlock Bypass Reset command is required to return to read
mode when device is in unlock bypass mode.
3. Shaded cells indicate read cycles. All others are write cycles.
4. During unlock and command cycles, when lower address bits are
555 or 2AA as shown in table, address bits above A11 and data
bits above DQ7 are don’t care.
5. No unlock or command cycles required when device is in read
mode.
6. Reset command is required to return to read mode (or to erase-
suspend-read mode if previously in Erase Suspend) when device
is in autoselect mode, or if DQ5 goes high while device is
providing status information.
15. System may read and program in non-erasing sectors, or enter
autoselect mode, when in Erase Suspend mode. Erase Suspend
command is valid only during a sector erase operation.
16. Erase Resume command is valid only during Erase Suspend
mode.
7. Fourth cycle of the autoselect command sequence is a read
cycle. Data bits DQ15–DQ8 are don’t care. Except for RD, PD
and WC. See Autoselect Command Sequence section for more
information.
8. Device ID must be read in three cycles.
17. Command is valid when device is ready to read array data or
when device is in autoselect mode.
18. Refer to Table 14, AutoSelect Codes for individual Device IDs
per device density and model number.
9. If WP# protects highest address sector, data is 98h for factory
locked and 18h for not factory locked. If WP# protects lowest
address sector, data is 88h for factory locked and 08h for not
factor locked.
April 30, 2004 S29GLxxxM_00A5
S29GLxxxM MirrorBitTM Flash Family
113
SPANSION [ SPANSION ]
