D a t a S h e e t
Table 19. Power-Up Sequence Timings
Parameter
Description
Speed
Unit
Reset Low Time from Rising Edge of V (or last Reset pulse) to Rising Edge
CC
of RESET#
t
Min
35
µs
VCS
Reset Low Time from Rising Edge of V (or last Reset pulse) to Rising Edge
IO
t
Min
35
µs
ns
VIOS
of RESET#
t
Reset High Time Before Read
Max
200
RH
Notes:
1.
V
< V + 200 mV.
IO
CC
2.
V
and V ramp must be in sync during power up. If RESET# is not stable for 35 µs, the following conditions may occur: the device does
IO
CC
not permit any read and write operations, valid read operations return FFh, and a hardware reset is required.
3. Maximum V power up current is 20 mA (RESET# =V ).
CC
IL
Vcc_min
Vio_min
VCC
VIO
tRH
CE#
tVIOS
tVCS
RESET#
Figure 22. Power-On Reset Timings
S29GL-N_00_B3 October 13, 2006
S29GL-N MirrorBit™ Flash Family
91
SPANSION [ SPANSION ]
