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S29JL064H55TFN000 参数 Datasheet PDF下载

S29JL064H55TFN000图片预览
型号: S29JL064H55TFN000
PDF下载: 下载PDF文件 查看货源
内容描述: 64兆位(8M ×8位/ 4米x 16位) CMOS 3.0伏只,同步读/写闪存 [64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory]
分类和应用: 闪存
文件页数/大小: 64 页 / 1399 K
品牌: SPANSION [ SPANSION ]
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P r e l i m i n a r y  
apply to the chip erase command.) If additional sectors are selected for erasure,  
the entire time-out also applies after each additional sector erase command.  
When the time-out period is complete, DQ3 switches from a “0” to a “1.” If the  
time between additional sector erase commands from the system can be as-  
sumed to be less than 50 µs, the system need not monitor DQ3. See also the  
Sector Erase Command Sequence section.  
After the sector erase command is written, the system should read the status of  
DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted  
the command sequence, and then read DQ3. If DQ3 is “1,the Embedded Erase  
algorithm has begun; all further commands (except Erase Suspend) are ignored  
until the erase operation is complete. If DQ3 is “0,the device will accept addi-  
tional sector erase commands. To ensure the command has been accepted, the  
system software should check the status of DQ3 prior to and following each sub-  
sequent sector erase command. If DQ3 is high on the second status check, the  
last command might not have been accepted.  
Table 9 shows the status of DQ3 relative to the other status bits.  
Table 9. Write Operation Status  
DQ7  
DQ5  
DQ2  
Status  
(Note 2)  
DQ6  
(Note 1)  
DQ3  
N/A  
1
(Note 2)  
RY/BY#  
Embedded Program Algorithm  
Embedded Erase Algorithm  
Erase  
DQ7#  
0
Toggle  
Toggle  
0
0
No toggle  
Toggle  
0
0
Standard  
Mode  
1
No toggle  
0
N/A  
Toggle  
1
Suspended Sector  
Erase-Suspend-  
Read  
Erase  
Suspend  
Mode  
Non-Erase  
Suspended Sector  
Data  
Data  
Data  
0
Data  
N/A  
Data  
N/A  
1
0
Erase-Suspend-Program  
DQ7#  
Toggle  
Notes:  
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing  
limits. Refer to the section on DQ5 for more information.  
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further  
details.  
3. When reading write operation status bits, the system must always provide the bank address where the Embedded  
Algorithm is in progress. The device outputs array data if the system addresses a non-busy bank.  
March 26, 2004 S29JL064HA1  
S29JL064H  
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