CY2210
Function Table
[2]
SEL133
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
SEL1
0
1
0
1
0
1
0
1
SEL0
CPUCLK
(MHz)
Hi-Z
100.227
[3]
100
100
TCLK/2
N/A
133.33
133.33
CPUCLK/2
(MHz)
Hi-Z
50.114
[3]
50
50
TCLK/4
N/A
66.67
66.67
AGPCLK
(MHz)
Hi-Z
66.818
[3]
66.67
66.67
TCLK/4
N/A
66.67
66.67
PCICLK
(MHz)
Hi-Z
33.409
[3]
33.33
33.33
TCLK/8
N/A
33.33
33.33
USBCLK
(MHz)
Hi-Z
48.008
[3]
OFF
48
TCLK/2
N/A
OFF
48
REFCLK
(MHz)
Hi-Z
14.318
[3]
14.318
14.318
TCLK
N/A
14.318
14.318
APICCLK
(MHz)
Hi-Z
16.705
[3]
16.67
16.67
TCLK/16
N/A
16.67
16.67
Actual Clock Frequency Values
Target
Frequency
(MHz)
-2
100.0
133.33
48.0
-3
100.0
133.33
48.0
-4
100.0
133.33
48.0
-2
99.126
132.769
48.008
Actual
Frequency
(MHz)
-3
99.126
132.769
48.008
-4
100.227
132.769
48.008
-2
–8740
–4208
167
PPM
-3
–8740
–4208
167
-4
+2714
–4208
167
Clock
Output
CPUCLK
CPUCLK
USBCLK
Clock Enable Configuration
CPU_STOP
X
0
0
1
1
PWR_DWN
0
1
1
1
1
PCI_STOP
X
0
1
0
1
CPUCLK
LOW
LOW
LOW
ON
ON
CPUCLK/2
LOW
ON
ON
ON
ON
AGP
LOW
LOW
LOW
ON
ON
PCI
LOW
LOW
ON
LOW
ON
PCI_F
LOW
ON
ON
ON
ON
REF
APIC
LOW
ON
ON
ON
ON
OSC.
OFF
ON
ON
ON
ON
VCOs
OFF
ON
ON
ON
ON
Clock Driver Impedances
Impedance
Minimum
Buffer Name
CPU, CPU/2, APIC
USB, REF
PCI, AGP
V
DD
Range
2.375–2.625
3.135–3.465
3.135–3.465
Buffer Type
Type 1
Type 3
Type 5
13.5
20
12
29
40
30
45
60
55
Typical
Maximum
Notes:
2. TCLK is a test clock driven in on the XTALIN input in test mode.
3. Only CY2210-2 supports this option. In CY2210-3, this selection is defined as “N/A” or “Reserved”.
Rev 1.0, November 25, 2006
Page 3 of 10
SPECTRALINEAR [ SPECTRALINEAR INC ]
