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CY2277APVC-1 参数 Datasheet PDF下载

CY2277APVC-1图片预览
型号: CY2277APVC-1
PDF下载: 下载PDF文件 查看货源
内容描述: Pentium㈢ / II , 6X86 , K6时钟合成器/驱动器,用于桌面/移动PC与Intel㈢ 82430TX和2个DIMM或3 SO- DIMM内存模块 [Pentium㈢/II, 6x86, K6 Clock Synthesizer/Driver for Desktop/ Mobile PCs with Intel㈢ 82430TX and 2 DIMMs or 3 SO-DIMMs]
分类和应用: 晶体驱动器外围集成电路光电二极管PC时钟
文件页数/大小: 18 页 / 293 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
 浏览型号CY2277APVC-1的Datasheet PDF文件第6页浏览型号CY2277APVC-1的Datasheet PDF文件第7页浏览型号CY2277APVC-1的Datasheet PDF文件第8页浏览型号CY2277APVC-1的Datasheet PDF文件第9页浏览型号CY2277APVC-1的Datasheet PDF文件第11页浏览型号CY2277APVC-1的Datasheet PDF文件第12页浏览型号CY2277APVC-1的Datasheet PDF文件第13页浏览型号CY2277APVC-1的Datasheet PDF文件第14页  
CY2277A  
Switching Characteristics (-1M, -7M, -12M)[9, 10, 11]  
Parameter  
Output  
Description  
Output Duty Cycle[12]  
Test Conditions  
t1 = t1A y t1B  
Min. Typ. Max.  
Unit  
t1  
CPUCLK  
SDRAM  
USBCLK  
REF [0,1]  
IOAPIC  
45  
50  
55  
%
t1  
t2  
PCI  
Output Duty Cycle[12]  
t1 = t1A y t1B  
45  
50  
55  
%
CPUCLK, CPU and IOAPIC Clock  
Between 0.4V and 2.0V, VDDCPU = 2.5V 0.60  
4.0  
V/ns  
IOAPIC  
PCI  
Rising and Falling Edge CPU clocks at 66.66 MHz  
Rate  
t2  
t2  
t2  
t2  
PCI Clock Rising and  
Falling Edge Rate  
Between 0.4V and 2.0V, VDDCPU = 2.5V 0.65  
4.0  
4.0  
4.0  
2.0  
V/ns  
V/ns  
V/ns  
V/ns  
USBCLK, USB, REF0 Clock Rising Between 0.4V and 2.4V  
and Falling Edge Rate  
0.65  
0.70  
0.5  
REF0  
SDRAM  
SDRAM Rising and  
Falling Edge Rate  
Between 0.4V and 2.4V  
SDRAM clocks at 66.66 MHz  
REF1  
REF1 Rising and Falling Between 0.4V and 2.4V  
Edge Rate  
t3  
t3  
t4  
t4  
t5  
t5  
t5  
CPUCLK  
USBCLK  
CPUCLK  
USBCLK  
CPUCLK  
PCICLK  
SDRAM  
CPU Clock Rise Time  
USB Clock Rise Time  
CPU Clock Fall Time  
USB Clock Fall Time  
CPU-CPU Clock Skew  
PCI-PCI Clock Skew  
Between 0.4V and 2.0V, VDDCPU = 2.5V 0.4  
Between 0.4V and 2.0V  
2.4  
2.5  
ns  
ns  
ns  
ns  
ps  
ps  
ps  
Between 2.0V and 0.4V, VDDCPU = 2.5V 0.4  
Between 2.0V and 0.4V  
2.4  
2.5  
Measured at 1.25V, VDDCPU = 2.5V  
Measured at 1.5V  
100  
2.0  
250  
400  
300  
SDRAM-SDRAM Clock  
Skew  
Measured at 1.5V  
t6  
t6  
t7  
CPUCLK, CPU-PCI Clock Skew  
PCICLK -1M, -12M  
Measured at 1.25V for 2.5V clocks, and  
at 1.5V for 3.3V clocks  
1.0  
6.0  
750  
600  
ns  
ps  
ps  
CPUCLK, CPU-PCI Clock Skew  
PCICLK -7M  
Measured at 1.25V for 2.5V clocks, and  
at 1.5V for 3.3V clocks  
CPUCLK, CPU-SDRAM Clock  
Measured at 1.25V for 2.5V clocks, and  
at 1.5V for 3.3V clocks, VDDCPU = 2.5V  
SDRAM  
CPUCLK  
SDRAM  
PCICLK  
Skew  
t8  
t8  
t8  
t8  
Cycle-Cycle Clock Jitter Measured at 1.25V for 2.5V clocks  
Cycle-Cycle Clock Jitter Measured at 1.5V  
525  
600  
400  
900  
ps  
ps  
ps  
ps  
Cycle-Cycle Clock Jitter Measured at 1.5V  
USBCLK, Cycle-Cycle Clock Jitter Measured at 1.5V  
IOCLK  
t9  
CPUCLK, Power-up Time  
PCICLK,  
SDRAM  
CPU, PCI, and SDRAM clock stabili-  
zation from power-up  
3
ms  
t10  
CPU, PCI, Frequency Slew Rate  
SDRAM  
Rate of change of frequency  
2
MHz/  
ms  
Rev 1.0,November 25, 2006  
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