CY28316
Table 6. Register Summary
Name
Description
WD_TIMER[4:0]
These bits store the time-out value of the Watchdog Timer. The scale of the timer is determine by the
prescaler. The timer can support a value of 150 ms to 4.8 sec when the prescaler is set to 150 ms. If
the prescaler is set to 2.5 sec, it can support a value from 2.5 sec to 80 sec. When the Watchdog Timer
reaches “0,” it will set the WD_TO_STATUS bit.
WD_PRE_SCALER
RST_EN_WD
0 = 150 ms.
1 = 2.5 sec.
This bit will enable the generation of a Reset pulse when a watchdog timer time-out occurs.
0 = Disabled.
1 = Enabled.
RST_EN_FC
This bit will enable the generation of a Reset pulse after a frequency change occurs.
0 = Disabled.
1 = Enabled.
How to Program CPU Output Frequency?
When the programmable output frequency feature is enabled
(Pro_Freq_EN bit is set), the CPU output frequency is deter-
mined by the following equation:
The ratio of (N+3) and (M+3) needs to be greater than “1”
[(N+3)/(M+3) > 1].
Table lists set of N and M values for different frequency output
ranges. This example uses a fixed value for the M-Value
Register and selects the CPU output frequency by changing
the value of the N-Value Register.
Fcpu = G * (N+3)/(M+3).
“N” and “M” are the values programmed in the Programmable
Frequency Select N-Value Register and M-Value Register,
respectively.
“G” stands for the PLL Gear Constant, which is determined by
the programmed value of FS[4:0] or SEL[4:0]. The value is
listed in Table 3.
Table 7. Examples of N and M Value for Different CPU Frequency Range
Fixed Value for
Range of N-Value Register
for Different CPU Frequency
Frequency Ranges
50 MHz – 129 MHz
130 MHz – 248 MHz
Gear Constants
M-Value Register
48.00741
93
45
97–255
48.00741
127–245
Rev 1.0,November 20, 2006
Page 12 of 17
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