CY28316
Byte 7: Control Register 7
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
–
25
26
–
–
–
–
–
Name
Reserved
24_48MHz_DRV
48MHz_DRV
Reserved
Reserved
Reserved
Reserved
Reserved
Default
0
1
1
0
0
0
0
0
Reserved.
0 = Norm, 1 = High Drive.
0 = Norm, 1 = High Drive.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Pin Description
Byte 8: Vendor ID and Revision ID Register (Read Only)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Revision_ID3
Revision_ID2
Revision_ID1
Revision_ID0
Vendor_ID3
Vendor_ID2
Vendor _ID1
Vendor _ID0
Default
0
0
0
0
1
0
0
0
Revision ID bit[3].
Revision ID bit[2].
Revision ID bit[1].
Revision ID bit[0].
Bit[3] of Cypress’s Vendor ID. This bit is read-only.
Bit[2] of Cypress’s Vendor ID. This bit is read-only.
Bit[1] of Cypress’s Vendor ID. This bit is read-only.
Bit[0] of Cypress’s Vendor ID. This bit is read-only.
Pin Description
Byte 9: System RESET and Watchdog Timer Register
Bit
Bit 7
Name
SDRAM_DRV
Default
0
Pin Description
SDRAM clock output drive strength.
0 = Normal.
1 = High Drive.
PCI clock output drive strength.
0 = Normal.
1 = High Drive.
Reserved
This bit will enable the generation of a Reset pulse when a Watchdog Timer
time-out occurs.
0 = Disabled.
1 = Enabled.
This bit will enable the generation of a Reset pulse after a frequency change
occurs.
0 = Disabled.
1 = Enabled.
Watchdog Timer Time-out Status bit.
0 = No time-out occurs (Read); Ignore (Write).
1 = Time-out occurred (Read); Clear WD_TO_STATUS (Write).
0 = Stop and reload Watchdog Timer. Unlock CY28316 from recovery frequency
mode.
1 = Enable Watchdog Timer. It will start counting down after a frequency change
occurs.
Note:
CY28316 will generate a system Reset, reload a recovery frequency, and
lock itself into a recovery frequency mode after a Watchdog Timer time-out
occurs. Under recovery frequency mode, CY28316 will not respond to any
attempt to change output frequency via the SMBus control bytes. System
software can unlock CY28316 from its recovery frequency mode by clearing the
WD_EN bit.
Bit 6
PCI_DRV
0
Bit 5
Bit 4
Reserved
RST_EN_WD
0
0
Bit 3
RST_EN_FC
0
Bit 2
WD_TO_STATUS
0
Bit 1
WD_EN
0
Rev 1.0, November 20, 2006
Page 7 of 17
SPECTRALINEAR [ SPECTRALINEAR INC ]
