CY28331
Table 4. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
2:8
9
10
11:18
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Command Code – 8 bits
'1xxxxxxx' stands for byte operation, bits[6:0] of the
command code represents the offset of the byte to be
accessed
Acknowledge from slave
Data byte from master – 8 bits
Acknowledge from slave
Stop
Description
Bit
1
2:8
9
10
11:18
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Command Code – 8 bits
'1xxxxxxx' stands for byte operation, bits[6:0] of the
command code represents the offset of the byte to
be accessed
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read = 1
Acknowledge from slave
Data byte from slave – 8 bits
Not Acknowledge
Stop
Byte Read Protocol
Description
19
20:27
28
29
19
20
21:27
28
29
30:37
38
39
Serial Control Registers
Byte 0: Frequency and Spread Spectrum Control Register
Bit
7
@Pup
Inactive = 0
Pin#
Name
Description
Write Disable (write once). A 1 written to this bit after a 1 has been written to Byte0
bit0 will permanently disable modification of all configuration registers until the part
has been powered off. Once the clock generator has been Write Disabled, the
SMBus controller should still accept and acknowledge subsequent write cycles but
it should not modify any of the registers.
For Test, always program to ‘0’
12
31
45
48
1
PCI33_7
FS3
FS2
FS1
FS0
Enable (1 = Enabled, 0 = Disabled)
corresponds to Frequency Selection. See
Table 1.
corresponds to Frequency Selection. See
Table 1.
corresponds to Frequency Selection. See
Table 1.
corresponds to Frequency Selection. See
Table 1.
Write Enable. A 1 written to this bit after power-up will enable modification of all
configuration registers and subsequent 0's written to this bit will disable modification
of all configuration except this single bit. Note that block write transactions to the
interface will complete, however unless the interface has been previously unlocked,
the writes will have no effect. The effect of writing this bit doe not take effect until
the subsequent block write command.
6
5
4
3
2
1
0
0
1
FS3 pin
FS2 pin
FS1 pin
FS0 pin
Inactive = 0
Byte 1: PCI Clock Control Register
Bit
7
6
5
4
3
2
1
@Pup
1
1
1
1
1
1
1
Pin#
23
24
22
21
18
17
14
Name
PCI33_F
PCI33_6
PCI33_5
PCI33_4
PCI33_3
PCI33_2
PCI33_1
Description
Enable (1 = Enabled, 0 = Disabled)
Enable (1 = Enabled, 0 = Disabled)
Enable (1 = Enabled, 0 = Disabled)
Enable (1 = Enabled, 0 = Disabled)
Enable (1 = Enabled, 0 = Disabled)
Enable (1 = Enabled, 0 = Disabled)
Enable (1 = Enabled, 0 = Disabled)
Rev 1.0, November 24, 2006
Page 4 of 16
SPECTRALINEAR [ SPECTRALINEAR INC ]
