CY28331
AC Electrical Specifications (continued)
PCI133_HT66 = 66MHz
Parameter
Description
Output Impedance
Test Condition
Min.
Typ.
Max. Unit
RON
Average value during switching transition
20
24
60
W
USB, 24_48 Clock Outputs
VOL
VOH
IOL
Output Low Voltage
Output High Voltage
Output Low Current
Output High Current
Frequency Actual
IOL = 9.0 mA
IOH = –12.0 mA
VO = 0.8V
0.4
V
V
2.4
16
mA
mA
MHz
MHz
V/ns
V/ns
%
IOH
VO = 2.0V
–22
F33
24.004
48.008
F66
tR
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Measured from 20% to 80%
Measured from 80% to 20%
Measured at 1.5V
0.5
0.5
45
2
2
tF
tD
55
TCCJ
TCCJ
TLTJ
TSTABLE
24_48MHz Cycle-to-Cycle Jitter
USB Cycle-to-Cycle Jitter
Long-term Jitter
Measured at 1.5V
0
250
500
200
1000
3
ps
Measured at 1.5V
0
ps
Measured at 1.5V
–1000
0
ps
Frequency Stabilization from
Power-up
Measure from full supply voltage
ms
RON
Output Impedance
Average value during switching transition
20
24
60
W
Table 6. Skew [2]
Parameter
Description
Conditions
Skew Window Unit
TSK_CPU_CPU
CPU to CPU skew, time independent Measured @ crossing points for CPUT rising
edges1
250
500
500
500
500
500
200
200
ps
ps
ps
ps
ps
ps
ps
ps
TSK_CPU_PCI33
CPU to PCI33 skew, time
independent
Measured @ crossing points for CPUT rising
edge and 1.5V PCI clocks
TSK_PCI33_PCI33 PCI33 to PCI33 skew, time
independent
Measured between rising @ 1.5V
TSK_PCI33_HT66 PCI33 to HT66 skew, time
independent
Measured between rising @ 1.5V
TSK_CPU_HT66
TSK_HT66_HT66
TSK_CPU_CPU
TSK_CPU_PCI33
CPU to HT66 skew, time
independent
Measured @ crossing points for CPUT rising
edge and 1.5V for HyperTransport clocks
HT66 to HT66 skew, time
independent
Measured between rising @ 1.5V
CPU to CPU skew, time variant
Measured @ crossing points for CPUT rising
edges
CPU to PCI33 skew, time variant
Measured @ crossing points for CPUT rising
edge and 1.5V PCI clocks
TSK_PCI33_PCI33 PCI33 to PCI33 skew, time variant Measured between rising @ 1.5V
200
200
200
ps
ps
ps
TSK_PCI33_HT66 PCI33 to HT66 skew, time variant
Measured between rising @ 1.5V
TSK_CPU_HT66
CPU to HT66 skew, time variant
Measured @ crossing points for CPUT rising
edge and 1.5V for HyperTransport clocks
TSK_HT66_HT66
HT66 to HT66 skew, time variant
Measured between rising @ 1.5V
200
ps
Note:
2. All skews in this skew budget are measured from the first referenced signal to the next. Therefore, this skew specifies the maximum SKEW WINDOW between
these two signals to be 500 ps whether the CPU crossing leads or lags the PCI clock. This should NOT be interpreted to mean that the PCI33 edge could either
be 500 ps before the CPU clock to 500 ps after the clock, thus defining a 1000ps window in which the PCI33 clock edge could fall.
Rev 1.0,November 24, 2006
Page 13 of 16
SPECTRALINEAR [ SPECTRALINEAR INC ]
