CY28331
Pin Description
Pin
3
4
41, 37
40, 36
XIN
XOUT
CPUT(0:1)
CPUC(0:1)
Name
PWR
V
DD
V
DD
V
DDC
V
DDC
I/O
I
O
O
O
O
I/O
Description
Oscillator Buffer Input.
Connect to a crystal or to an external clock.
Oscillator Buffer Output.
Connect to a crystal. Do not connect when an
external clock is applied at XIN.
CPU clock outputs 0 and 1:
push-pull “true” output of differential pair.
CPU clock outputs 0 and 1:
push-pull “complement” output of differential
pair.
3.3V PCI clock outputs controlled by PCISTOP#.
PCISel is a strap option during power-up to select Pin 24 functionality:
0: Configure Pin 24 as PCI33_6
1: Configure Pin 24 as PCISTOP# (default 100k internal pull-up)
After power-up, this pin reverts to standard PCI33_F output.
3.3V PCI 33 MHz or HyperTransport 66 clock outputs.
This group is
selectable between 33 MHz and 66 MHz, based on the state of
PCI33HT66SEL[0:1]#.
PCI33 or HT66 select.
This input strap selects the output frequency of
PCI33_HT66 outputs to either 33 MHz or 66 MHz. There is an internal
100Kohm pull-up resistor. After power-up, this pin becomes
PCI33_HT66_[0:1] output.
SEL1
SEL0 PIN6
PIN7
PIN8
PIN11
0
0
HT66_0
HT66_1 HT66_2
HT66_3
0
1
HT66_0
HT66_1 HT66_2
PCI33_3
1
0
HT66_0
HT66_1
PCI33_2
PCI33_3
1
1
HT66_0
PCI33_1 PCI33_2
PCI33_3
3.3V USB clock output at 48 MHz.
At power-up this pin is sensed to
determine the CPU output frequency. There is an internal 100K-ohm
pull-down resistor.
3.3V super I/O clock output.
At power-up this pin is sensed to determine
whether the output is 24 MHz or 48 MHz. There is an internal 100K-ohm
pull-down resistor. This pin will be externally strapped high using a
10K-ohm resistor to V
SS
. 0 = 48 MHz, 1 = 24 MHz.
3.3V reference clock output.
At power-up this pin is sensed to determine
the CPU output frequency. There is an internal 100K-ohm pull-up resistor
for FS0, while FS(1:2) includes 100K ohm pull-up resistors.
Watchdog Time-out Reset Output.
Power-down input (100K internal
pull-up).
When configured through pin 23 as PCI_STOP#, this pin controls the
PCI33(0:5,7) and PCI33_HT66(1:3) outputs.
Active LOW control input to
halt all 33-MHz PCI clocks except PCI33_F. Only the PCI33_HT66 outputs
that are running at 33 MHz will be stopped. The outputs will be glitch-free
when turning off and turning on (100K internal pull-up). When configured
through pin 23 as PCI33_6, PCI_STOP# is unavailable.
3.3V PCI clock outputs controlled by PCISTOP#.
Data pin for SMBus (rev2.0).
There is an internal 100K-ohm pull-up
resistor.
Clock pin for SMBus (rev2.0).
There is an internal 100K-ohm pull-up
resistor.
13, 14, 17, PCI33(0:5)
18, 21, 22
23
PCISel /
PCI33_F
8, 11
PCI33_HT66(2:3)
V
DDD
O
6, 7
PCI33_HT66_[0:1]/
PCI33_HT66SEL[0:1]#
V
DDD
I/O
31
USB/FS3
I/O
28
24_48MHz/SEL#
I/O
1, 48, 45
REF(0:2)/FS(0:2)
I/O
44
24
SRESET#/PD#
PCI33_6/
PCISTOP#
I/O
I/O
12
26
25
PCI33_7
SDATA
SCLK
O
I/O
I
V
DD
2, 9, 16,
19, 29, 35,
38, 46
5, 10, 15, V
SS
20, 27, 30,
34, 39, 47
PWR
Power connection to 3.3V for the core.
GND
Power connection to GROUND for the CORE section of the chip.
Rev 1.0, November 24, 2006
Page 2 of 16
SPECTRALINEAR [ SPECTRALINEAR INC ]
