CY28341-3
VID (0:3),
SEL (0,1)
VTT_PWRGD#
PW RGD
0.2-0.3mS
Delay
Wait for
VTT_GD#
Sample Sels
State 2
VDD Clock Gen
Clock State
State 0
Off
State 1
State 3
(See Note 3)
On
Clock Outputs
Clock VCO
On
Off
Figure 6. VTT_PWGD# Timing Diagram (with P4 Mode, SelP4_K7 = 1)[3]
S 1
S 2
W a it fo r
1 .1 4 6 m s
S a m p le
In p u ts
F S (3 :0 )
E n a b le
O u tp u te s
D e la y 0 .2 5 m S
V D D A = 2 .0 V
S 0
S 3
N o rm a l
O p e ra tio n
P o w e r O ff
V D D 3 .3 = O ff
Figure 7. Clock Generator Power-up/Run State Diagram (with P4 Processor SELP4_K7#=1)
Connection Circuit DDRT/C Signals
For open-drain CPU output signals (with K7 processor
SELP4_K7#=0)
VDDCPU(1.5V)
500 Ohm
VDDCPU(1.5V)
3.3V
Measurement Point
ꢁꢂꢃꢀOhm
ꢂꢄꢀOhmꢀꢀ5"
60.4 Ohm
47 Ohm
ꢂꢄꢀOhmꢀꢀꢁ"
CPUOD_T
680 pF
20 pF
500 Ohm
3.3V
301 Ohm
ꢁꢂꢃꢀOhm
ꢂꢄꢀOhmꢀꢀ5"
VDDCPU(1.5V)
ꢂꢄꢀOhmꢀꢀ1"
47 Ohm
500 Ohm
CPUOD_C
Measurement Point
680 pF
60.4 Ohm
20 pF
500 Ohm
VDDCPU(1.5V)
Figure 8. K7 Load Termination
Note:
3. This time diagram shows that VTT_PWRGD# transits to a logic low in the first time at power-up. After the first high-to-low transition of VTT_PWRGD#, device is
not affected, VTT_PWRGD# is ignored.
Rev 1.0,November 21, 2006
Page 12 of 19
SPECTRALINEAR [ SPECTRALINEAR INC ]
