CY28341-3
Byte 5: SDR/DDR Clock Register
(continued)
Bit
4
3
2
1
0
@Pup
1
1
1
1
1
Pin#
31,32
35,36
37,38
41,42
43,44
Name
DDRT/C4
DDRT/C3
DDRT/C2
DDRT/C1
DDRT/C0
Description
1 = output enabled (running). 0 = output disabled asynchronously in a low state.
1 = output enabled (running). 0 = output disabled asynchronously in a low state.
1 = output enabled (running). 0 = output disabled asynchronously in a low state.
1 = output enabled (running). 0 = output disabled asynchronously in a low state.
1 = output enabled (running). 0 = output disabled asynchronously in a low state.
Byte 6: Watchdog Register
Bit
7
@Pup
0
Pin#
26
Name
SRESET#
Description
1 = Pin 26 is the input pin as PD# signal. 0 = Pin 26 is the output pin as
SRESET# signal.
This bit allows setting the Revert Frequency once the system is rebooted
due to Watchdog time out only. 0 = select frequency of existing H/W setting,
1 = select frequency of the second to last S/W table setting. (the software
setting prior to the one that caused a system reboot).
For IMI Test - WD-Test, ALWAYS program to '0'
This bit is set to “1” when the Watchdog times out. It is reset to “0” when the
system clears the WD time stamps (WD3:0).
This bit allows the selection of the time stamp for the Watchdog timer. See
Table 7
This bit allows the selection of the time stamp for the Watchdog timer. See
Table 7
This bit allows the selection of the time stamp for the Watchdog timer. See
Table 7
This bit allows the selection of the time stamp for the Watchdog timer. See
Table 7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Frequency Revert
WDTEST
WD Alarm
WD3
WD2
WD1
WD0
Table 7. Watchdog Time Stamp
WD3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
WD2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
WD1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
WD0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Off
1 second
2 seconds
3 seconds
4 seconds
5 seconds
6 seconds
7 seconds
8 seconds
9 seconds
10 seconds
11 seconds
12 seconds
13 seconds
14 seconds
15 seconds
FUNCTION
Rev 1.0, November 21, 2006
Page 7 of 19
SPECTRALINEAR [ SPECTRALINEAR INC ]
