CY28341-2
Byte 2: PCI Clock Register
Bit
7
6
5
4
3
2
1
0
@Pup
0
1
1
1
1
1
1
1
10
18
17
15
14
12
11
Pin#
Name
PCI_DRV
PCI_F
PCI6
PCI5
PCI4
PCI3
PCI2
PCI1
Description
PCI clock output drive strength 0 = Low strength, 1 = High strength
1 = Output enabled (running). 0 = Output disabled asynchronously in a low state.
1 = Output enabled (running). 0 = Output disabled asynchronously in a low state.
1 = Output enabled (running). 0 = Output disabled asynchronously in a low state.
1 = Output enabled (running). 0 = Output disabled asynchronously in a low state.
1 = Output enabled (running). 0 = Output disabled asynchronously in a low state.
1 = Output enabled (running). 0 = Output disabled asynchronously in a low state.
1 = Output enabled (running). 0 = Output disabled asynchronously in a low state.
Byte 3: AGP/Peripheral Clocks Register
Bit
7
6
5
4
3
2
1
0
@Pup
0
1
1
0
0
1
1
1
Pin#
21
20
21
6,7,8
6,7,8
8
7
6
Name
24_48M
48MHz
24_48M
DASAG1
DASAG0
AGP2
AGP1
AGP0
Description
0 = pin21 output is 24 MHz. Writing a '1' into this register asynchronously
changes the frequency at pin21 to 48 MHz.
1 = Output enabled (running). 0 = Output disabled asynchronously in a low state.
1 = Output enabled (running). 0 = Output disabled asynchronously in a low state.
Programming these bits allow shifting skew of the AGP(0:2) signals relative to
their default value. See
Table 5.
1 = Output enabled (running). 0 = Output disabled asynchronously in a low state.
1 = Output enabled (running). 0 = Output disabled asynchronously in a low state.
1 = Output enabled (running). 0 = Output disabled asynchronously in a low state.
Table 5. Dial-a-Skew
DASAG (1:0)
00
01
10
11
AGP(0:2)
AGP(0:2) Skew Shift
Default
–280 ps
+280 ps
+480 ps
Byte 4: Peripheral Clocks Register
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
0
0
1
1
1
1
Pin#
20
21
6,7,8
6,7,8
1
56
1
56
48M
24_48M
DARAG1
DARAG0
REF0
REF1
REF0
REF1
Name
Description
1 = Low strength, 0 = High strength
1 = strength x 1. 0= strength x 2
1 = Low strength, 0 = High strength
1 = strength x 1. 0= strength x 2
Programming these bits allow modifying the frequency ratio of the AGP(2:0),
PCI(6:1, F) clocks relative to the CPU clocks. See
Table 6.
1 = Output enabled (running). 0 = Output disabled asynchronously in a low state.
1 = Output enabled (running). 0 = Output disabled asynchronously in a low state.
1 = Low strength, 0 = High strength
1 = Low strength, 0 = High strength (K7 Mode only)
Table 6. Dial-A-Ratio
DARAG (1:0)
00
01
10
11
AGP(0:2)
CU/AGP Ratio
Frequency Selection Default
2/1
2.5/1
3/1
Rev 1.0, November 21, 2006
Page 6 of 18
SPECTRALINEAR [ SPECTRALINEAR INC ]
